Study And Fabrication Of SOI/SiGe MOS Device

This article is mainly about the SiGe hetrojunction MOS device fabricated by SOI technology. The hetrojunction device fabricated with SiGe material has shown great advantages over bulk sample in many aspects: higher carrier mobility, larger transconductance, stronger drive capability and hence faster circuit speed. Here we take the strained Si cap layer with relaxed SiGe layer grown epitaxially by UHVCVD to form NMOSFET and relaxed Si cap layer with strained SiGe layer to form PMOSFET as comparison to bulk sample. From which we can draw a conclusion that the hole mobility can experience a 15% improvement in the strained SiGe layer while the electron mobility can experience a 48.5% improvement in the strained Si layer.In the second part, we introduce the advantages of SOI devices together with their corresponding mechanisms: free of latch-up effect, low parasitic capacitance, easy to form shallow junctions and so on. Then we studied the BMHMT method of SOI MOSFET and its merit: larger drive current which enables it to be the candidate of BJT in realizing BICMOS circuits. Besides exploration and understanding in theory, we also discussed about many design problems, including device design, 版图design and process parameter design problems. Moreover, we throw some supposes on those abnormal phenomenon and try to verify them by simulation.We simulated and adjusted the energy and dose of implant impurity by the aid of Silvaco software so as to confine the Vt value in a reasonable range and finally we got eligible device samples. According to the structure we designed, the SiGe material grown by UHV/CVD was analyzed by DCXRD, TEM, SIMS and AFM.