The Research On Energy Discrimination Module At Trigger System In Beijing Spectrometer

Beijing Spectrometer (BESIII), the National major Project at the Institute of High Energy Physics is approved and now the relative R&D and preliminary Designing are undergoing. The trigger system of BESIII is one of the most important parts of the real-time data acquisition system of BESIII, which must be studied and tested carefully before the final design .This paper summarizes the characteristic and structure of BEPCII ,BESIII ,and the The trigger system .The function of EMC and the energy discrimination module in the BESIII project is introduced .The energy of more trigger unit is added and discriminated in the energy discrimination module for the count of the next module (TCCNT).It is a process that analog signals are changed into digits signals and have a important postion in the trigger system.The frame of the energy discrimination module and its main circuit function is designed in this paper.The time extraction circuit is the main unit of the discrimination module and researched in this paper. Some of the signals from EMC Front-End electronics go to the energy discrimination module in trigger system, in which, if its energy is over the predefined threshold, an output signal is given at the time representing the time of signal arrival. The function of general pulse-height discriminator and its existing timing error (walk) which is brought from pulse-height and waveform influence were fitstly introduced in this paper, Based on the characteristic of EMC output signal in the actual case, the idea that one-polarity pulse signals become two-polarity pulse signals by LAP conversion was adopted . The zero of two-polarity pulse signal through CR differential which is not related to the pulse-height of one-polarity pulse signals by analysis may be a pivotal time point. a special designed time extraction circuit with zero-crossing technique has been studied and tested, and a energy discriminator is designed. The design is based on the result of PSPICE simulation and a test result of maximum timing error was obtained which is near the requirement in trigger system timing. The reading out of the output of this discriminator by VME bus in this module was also drafted. FPGA design was adopted in it because of its variety .