On the investigation of materials, technology, and testing of electrostatic discharge (ESD) protection for integrated circuits

Electrostatic Discharge (ESD) phenomena in Integrated Circuits (IC) have grown in importance as IC processing technology is pushed to the limit. Device under ESD stress operates well outside the realm of normal device operation. Circuit designers have largely ignored physics governing this region of operation as well as circuit design issues involved.; Over the years there has been much work done in the area of ESD circuit design and physics in digital CMOS circuits. However, very little attention has been paid on ESD protection research for Radio Frequency (RF) circuits and mix-mode circuits, making them much more sensitive to ESD damage. ESD protection trade-offs with normal circuit operations in these types of circuit are rarely addressed. Traditionally, it has been left to trial and error. In addition, as device dimension continues to shrink, the traditional ESD protection scheme for digital IC's faces new challenge. Traditional snapback transistors become obsolete as silicon dioxide breakdown voltage drops below the protection device trigger point. In order to address these new challenges in ESD protection networks in deep-submicron mix-mode circuits, new device structures and new figure of merit are defined. These protection networks mainly based on different diodes on their substantial ESD robustness and area efficiency. A simpler diode model under ESD operation regime is explored. Design criteria correlating diode reverse breakdown ESD robustness and layout is also found to further extend ESD protection network robustness.; AlGaAs/GaAs heterojunction bipolar transistors (HBTs) are finding increasing applications in analog, digital, and microwave circuits and have demonstrated superior power performance at microwave frequencies. While much work has been done to address the reliability issues on single emitter finger HBT's under normal operation conditions, only have a few reports focused on the electrical overstress issues-such as ESD events taking place during virtually any step of device processing, packaging, testing, and use. The effects of ballast resistors on design tradeoff between forward bias ESD robustness and peak power handling capability were studied for the first time in power AlGaAs/GaAs heterojunction bipolar transistors. It is found that though a ballast resistor prevents transistors from the current gain collapse to achieve a better thermal stability at higher power density, it can also significantly reduce the forward biased ESD performance of the ballasted junction. Ballast resistor ESD robustness is particularly important for integrated HBT's circuits when ESD stress happens between the input and output terminals. A design criterion for optimizing ESD survivability and output power is explored.; Long term reliability of part after ESD stress is a major issue. To identify the possibility of “walking-wounded” parts before a circuit is committed to mass production can significantly reduce the number of product returns. However, as process technology advances towards multi-layer metal interconnects, traditional techniques employed in identification of weak spot is pushed to their limits. Time consuming and expert-based techniques prohibit more systematic studies of “walking-wounded” parts. A novel technique involving highly selective removal of the silicon substrate is explored. More than one part can be studied in detail in order to understand the weak spot in an ESD protection network.