Poly-silicon-germanium gate technology and direct-tunneling oxide for deep-submicron CMOS application

Currently, some CMOS processes have implemented silicon-germanium (Si 1-xGex) as an ultra-shallow source/drain dopant diffusion source. Poly-Si1-xGex is also a promising alternative to poly-Si as a gate material due to its process compatibility and favorable electrical properties, such as lower sheet resistance, higher dopant activation rate, and tunable work-function. However, few detailed investigations have been made of the impact of a poly-Si1-xGex gate on device performance and reliability.; In this work, both N- and PMOS poly-Si1-xGex-gated devices were fabricated. The CV curves and electrical properties for different gate oxide thicknesses and implant doses were obtained. Active dopant concentration near the poly/SiO2 interface, gate-depletion width, and flat-band voltage were extracted. The work-function differences for both N+ and P+ Si1-xGex films were determined. The experimental results indicate that poly-Si1-xGex dual-gate CMOS performance can be optimized at ∼20% Ge content in terms of short-channel effects (SCE) and gate-depletion effects (GDE).; The tradeoff between boron penetration and GDE was compared between poly-Si and poly-Si0.8Ge0.2-gated devices. Not only were improved GDE found in boron-implanted poly-Si0.8Ge0.2-gated devices, but observations of smaller flat-band voltage shift and superior gate oxide reliability suggest less boron penetration in poly-Si0.8Ge 0.2-gated devices compared to poly-Si-gated devices. A larger process window therefore exists for a poly-Si0.8Ge0.2 gate technology with regard to the tradeoff between boron penetration and gate depletion.; Device performance and reliability were characterized for poly-Si 0.75Ge0.25- and poly-Si-gated CMOSFETs with physical channel lengths down to 0.1mum and gate oxide thicknesses down to 25A. The poly-SiGe-gated NMOS and PMOS devices provide superior current drive due to less GDE and higher inversion hole mobility in poly-SiGe-gated devices. In addition, gate oxide integrity in poly-SiGe-gated MOSFETs is as good as with poly-Si-gated devices. Poly-SiGe-gated PMOSFETs have better reliability than poly-Si-gated PMOSFETs due to reduction of boron penetration.; As gate oxide thickness is scaled below 30A, direct-tunneling current will dominate the gate leakage under normal device operation. To address this issue, poly-Si and poly-Si0.75Ge0.25-gated N/PMOS transistors with gate oxides of 25A and 29A are employed to determine the transport mechanisms under different bias conditions. The significance of the hole direct-tunneling, electron direct-tunneling and electron-hole pair generation components were investigated by charge-separation measurements.; A semi-empirical model is proposed to quantify the tunneling currents through ultra-thin gate oxides. With a proper set of effective mass and barrier height, this new model can be used to predict electron tunneling from the conduction band, electron tunneling from the valence band, and hole tunneling from the valence band in dual-gate CMOS devices with great accuracy. Extractions of gate oxide thickness and gate doping concentration from Ig-V g characteristics are also discussed.; Lastly, a novel self-aligned double-gate FinFET structure is implemented on SOI to suppress short-channel effects. This new variant of the vertical double-gate SOI MOSFETs exhibits excellent short-channel behavior in both NMOS and PMOS FinFETs with sub-20nm channel length. With planar process compatibility, this novel structure is very promising for scaling beyond 50nm and is suitable for terabit-scale integration.