Device and architecture co-design for ultra-low power logic using emerging tunneling-based devices

The scaling of silicon CMOS, by delivering lower switching-energy transistors with each technology generation, has been the driving force behind total circuit-energy reduction during the past three decades. However, during the past decade it has become increasingly challenging to achieve energy efficiency through scaling of conventional silicon CMOS. One of the key reasons that has caused this energy scaling challenge is the slowdown in VCC scaling, due to non-scalability of VT. The other reason is the steady increase in leakage power consumption with each technology generation due to worsening short channel effects. As the development of sub-22nm CMOS devices is currently underway, alternative transistor-architectures such as 3D tri-gate, and alternative novel semiconductor material systems such as III-V InGaAs (indium galium arsenide) are being considered to allow both continued feature size scaling as well as VCC scaling. However, some of these emerging transistors have unique properties which require conventional circuit and system design to be re-examined. In this context, co-design of novel devices and architecture, which is the topic of this dissertation, enables the drive toward continued energy reduction. In this dissertation, circuit and architecture-level design aspects for emerging low-VCC devices, such as the Single Electron Transistor (SET) and the Inter-band Tunneling Field Effect Transistor (TFET), are examined.;The energy-delay characteristics of low-VCC sub-300mV logic circuits based on nearly broken-gap GaSb-InAs (galium antimonide-indium arsenide) heterojunction TFETs, are modeled. By taking advantage of an energy-delay crossover behavior between silicon CMOS and heterojunction TFET logic circuits, a hybrid heterogeneous CMOS-TFET multi-core processor architecture is proposed. Simulated execution of several single and multi-threaded benchmark programs on this heterogeneous architecture shows significant energy-delay advantages compared to either a homogeneous CMOS or TFET multi-core processor alone. Device-level variability plays an important role in restricting the minimum operating voltage (VCC-min) at which a circuit can operate in a reliable manner. We have constructed a device-level variability model for TFETs and studied the impact of variation on TFET-based SRAM bit-cells. From this study, it is concluded that a Schmitt Trigger-based TFET SRAM bit-cell with a built-in feedback mechanism is most suitable for enabling ultra-low VCC operation of heterojunction TFET-based SRAM circuits. Following this, the asymmetric sub-threshold characteristics of degenerately-doped source (DDS) n-channel and p-channel III-V Tunnel FETs are examined. A TFET-based 4T-loadless SRAM cell is proposed, taking advantage of the asymmetric sub-threshold characteristics of n and p-channel TFETs, which shows improved performance and lower leakage compared to Si CMOS-based 4T-Loadless SRAM cells at low-V CC. A patent application has been filed based on the TFET-based 4T-loadless SRAM and a provisional patent has been approved. Finally, A design space based on physical dimensions and electrostatic properties is proposed to enable circuit-level analysis for SETs. Subsequent circuit-analysis shows that a Sense Amplifier-Binary Decision Diagram (SA-BDD) circuit-architecture, is most suitable to enable ultra low-VCC sub-150mV for practically realizable Single Electron Transistors, which have low self-gain.;These design studies show that it is necessary to model and study characteristics such as energy-delay performance and variability of emerging transistors, in order to enable ultra low-power circuit operation in the nanoscale regime.