| Si/SiO2 interface roughness has been related to the inversion layer carrier mobility degradation, gate dielectric reliability, gate leakage current, and ballistic transmittance, yet the quantitatively measurement of the Si/SiO2 interface has not been achieved at the nanometer scale. For the first time, we demonstrate that ultra-high vacuum scanning tunneling microscopy (UHV-STM) can be used to tunnel through 1-nm-thick industry-standard oxide to directly examine the Si/SiO2 interface and extract interface roughness parameters from the STM topography. Our results show that the interface roughness has a root mean square (rms) value of 0.285 nm and a correlation length of 2.42 nm for a gate oxide sample that has gone through a conventional shallow trench isolation process flow. We find that the autocovariance function has an exponential decay instead of a Gaussian decay. The corresponding electron and hole mobilities are measured and compared with the calculations of the mobilities that are completely constrained by the STM measured parameters. The concurrence between the measurements and calculations indicates that interface roughness scattering accounts for the measured mobility for effective transverse fields Eeff > 1.2 MV/cm. An industry standard shallow trench isolation process flow is examined to find out the process steps that affect the Si/SiO2 interface roughness. This knowledge is then used to modify the process flow for producing a smooth interface. Initial experiments indicate that the rms roughness can be reduced to 0.111 nm while keeping the correlation length practically unchanged with the modified process flow, and predict a factor of four mobility improvement in high transverse fields. Further process improvements are proposed with emphases on the pre-oxidation surface preparation, oxidation, and ion implantation steps, which can be easily incorporated into the current shallow trench isolation process flow. |
