Design methodologies for on-chip inductive interconnect

With the decrease in feature size of CMOS integrated circuits, interconnect design has become an important issue in high speed, high complexity integrated circuits (IC). Different design methodologies have been proposed to improve circuit performance. Wire sizing, driver sizing, and wire shaping are common techniques to enhance circuit performance.; With increasing signal frequencies and the corresponding decrease in signal transition times, the interconnect impedance can behave inductively. Different design methodologies under an inductive environment are described in this dissertation. Including line inductance in the design process can enhance both the delay and power as well as improve the accuracy of the overall design process.; Line inductance introduces new tradeoffs in interconnect and driver sizing to decrease the circuit delay. An accurate solution for the optimum line width is described that minimizes the total transient power dissipated by a CMOS circuit. Furthermore, interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process also saves gate area, reducing the dynamic power dissipation.; An alternative technique to reduce the propagation delay in long inter-connects is non-uniform wire sizing or wire shaping. In this dissertation, the optimum wire shape for the minimum signal propagation delay across an RLC line is shown to have a general exponential form. The line inductance makes exponential tapering more attractive in RLC lines than in RC lines. Wire tapering can reduce both the propagation delay and the power dissipation. This technique is used to size the interconnect lines within an H-tree clock distribution network. Exponentially tapered interconnect is shown to reduce the dynamic power dissipation while preserving the signal characteristics within clock distribution networks. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise.; On-chip inductance should be included in the design process in high frequency circuits. By including the on-chip inductance, the efficiency of different circuit design techniques such as wire sizing, driver sizing, and line tapering can be greatly enhanced.