Cache performance prediction for memory-intensive applications

The desire for large-size, high-speed and low-power on-chip memory necessitate early and accurate estimates of memory performance. Lacking an accurate memory performance estimator, a memory analytical model named PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack) has been developed for on-chip SRAM/DRAM cache design. PRACTICS' models are verified by Cadence simulations. In the delay model, the access time is estimated by decomposing each component into several equivalent lumped RC circuits and using an appropriate order pi model to approximate the distributed wire delays of each stage. The dynamic power model calculates the charging power dissipation of the load capacitances estimated from the same equivalent lumped RC circuits. An integrated version of PRACTICS considers the tradeoff between the access time and dynamic power consumption for SRAM. Based on the specified technology-dependent parameters, the program optimizes the memory array configuration parameters to minimize an evaluation function which contains delay and power considerations by running an exhaustive search algorithm. The delay models have been validated with industrial memory designs, achieving accuracy to within 10% of the measured results. The dynamic power model has been validated with an IBM SRAM design, to within 13% of the measured power consumption.; The PRACTICS model sensitivity is discussed in terms of the variations of peripheral logic circuit designs, active devices and interconnect parameters. In addition, PRACTICS is used to estimate the cache access speed and power consumption at different technology nodes. With a more complicated scaling approach than the linear scaling approach used in previous models, PRACTICS considers the scaling of active devices, wiring strategy and circuit parameters individually to obtain a more accurate predictive capability. Moreover, PRACTICS is extended to predict the performance advantages of wafer-level 3D integration. The performance comparisons between wafer-level 3D and conventional 2D designs shows wafer-level 3D integration has advantages of high speed, low power and high density. These results have important implications for the partitioning and packaging of memory-intensive systems, with large-size and high-speed on-chip memory being an effective driver for wafer-level 3D IC technology.