Thermal analysis and multiobjective optimization for three dimensional integrated circuits

Three Dimensional Integrated Circuit (3DIC) technology has been introduced to address the interconnect issues in nanometer circuit design that limit performance improvement and power reduction. However, stacking active layers of silicon leads to increased power density and overall higher temperatures in a 3D chip implementation for many designs. New thermal map modeling, and temperature measurement, mitigation and management techniques should be introduced for this technology. In this dissertation we study the thermal correlation between the stacked layers in 3DICs. We then propose a fast and efficient 3D thermal map modeling based on scaled hotspot areas, depending on the distance of a stacked layer from the heatsink and also thermal effects of the layers on each other. The modeling is 53x faster than the existing method of temperature compact modeling. The efficiency of the proposed modeling is demonstrated with its use in a thermal sensor distribution algorithm. We also show that the thermal sensor distribution algorithm should be solved as a 3D problem. In this way for the same sensor reading error the total number of needed sensors is reduced by 44%. We furthermore propose a new 3D design for thermal sensor circuits to be shared between layers in a 3DIC. Using 3D thermal sensors that are shared between adjacent layers can reduce the total number of needed sensors by half.;We also study different methods of multiobjective optimization to find the optimum operating point of a VLSI circuit. We provide wide mathematical analyses of different multiobjective optimization techniques for this purpose. We also study the difference of convex and non-convex modeling of the objectives in the multiobjective optimization algorithms.;We apply our multiobjective optimization methods to optimize three conflicting objectives of cost, performance and thermal reliability to find an optimum building block placement in 3DICs. The variables for the optimization are the number of layers, area of the 3DIC, position of the building blocks, number of TSVs and total wirelength. We used our proposed fast 3D thermal map modeling to eliminate the thermal analysis bottleneck in multiobjective optimization iterations. In comparison with a previous state-of-the-art multiobjective optimization method which employs Simulated Annealing, a weighted sum method of scalarization and compact modeling for thermal analysis, our method reduces the peak temperature of a representative 3DIC by 4.3% and total wire length by 5.7% while it is more than 17x faster in optimization runtime. The execution runtime of the proposed algorithm also scales linearly with problem size in contrast with the existing heuristic method of Simulated Annealing, which scales poorly with problem size.