Measurement, suppression, and prediction of digital switching noise coupling in mixed-signal system-on-chip applications

In System-on-Chip (SoC) applications the digital switching noise propagates through substrate and power distribution to analog circuits, degrading their performance. To overcome this issue, measurement, suppression, and prediction of noise coupling are essential. This research focuses on all these three aspects, by developing new and improved measurement techniques for substrate and power supply noise, by proposing novel suppression methods based on active noise cancellation, and by creating a modeling technique for early prediction of noise coupling in architectural stages of the design.; The measurement work proposes a substrate and power supply probing technique based on small and compact sensors that can easily be placed within high-density layout regions. Their outputs are multiplexed and routed to an on-chip digitizing waveform recorder. The on-chip digitizing reduces the bandwidth limitation and signal contamination due to off-chip routing, and eliminates additional analog output pins. Based on experimental evaluation on a 0.13 mum CMOS test chip, the bandwidth is useful from DC to 1.6 GHz, and the linearity is better than 1.5% for substrate, and 6% for power supply sensors.; The suppression work proposes active noise cancellation structures that can be used in addition to conventional guard ring methods. Coupling reduction for NMOS in common-source amplifier of 8.8 times has been achieved at 10 MHz sinusoidal substrate noise. Coupling reduction for NMOS common source with degeneration of 56 times has been achieved at 10 MHz. Ring oscillator sideband suppression of 25 dB has been achieved at 1 MHz sinusoidal substrate noise for differential delay cells with noise cancellation.; The prediction work first analyzes the coverage of existing techniques at various stages of the design process. It is emphasized that the most accurate methods use the complete layout which is available only late in the design process. However, problems found at this stage often require major rework that significantly impacts cost and schedule. Driven by the desire to predict noise coupling problems early in the design process, this work proposes a novel hybrid lumped-distributed model of the chip substrate and power distribution, integrated in a macro-model of the chip, package, and PCB.