Distributed effects in power transistors and the optimization of the layouts of aluminum gallium nitride/gallium nitride HFETs

The distributed effects on gate, drain and source for the one-finger FET (lateral distributed effects) are analyzed and analytical solutions are obtained. A 4-port network model is reported for the 6-terminal device in the limit of small device width. Negative gate, drain and source feedback impedances are observed in the 4-port network. Two boundary 2-port conditions are considered resulting in two distributed 2-port equivalent circuits in the limit of small width. For transistors with large periphery, distributed effects along gate and drain rails are analyzed. An analytical solution is presented in the small length approximation, which includes both distributed effects along the rails and the device width. From the solution, it is inferred that the distributed effects due to the rails become dominant as the number of gate fingers is increased.; The parasitic network of an AlGaN/GaN FET is studied using Momentum simulator. A Momentum simulation block for AlGaN/GaN HFETs is defined for a standard GaN process. In the simulation block, grounding is provided by vias. In order to extract the lateral impedances, Momentum simulations performed for the 4-port FET network, are fitted using the 4-port network model. The parasitics caused by the air-bridges are obtained and the effect on the device performance is examined. The scalability of the device is examined by comparing lateral impedances of 50mum, 100mum, 150mum, 200mum, 250mum and 300mum wide AlGaN/GaN HFETs.; The Agere Electro-thermal Transistor (AET) model is modified to fit the AlGaN/GaN HFET. The DC-IV model is extracted from measured pulsed-IV for a 2-finger 150mum AlGaN/GaN HFET on sapphire provided by AFRL. The small signal model is extracted to obtain operating frequencies of 11.7GHz and 48.2GHz. A center-fed transistor and an edge-fed transistor are first investigated to implement the 11.7GHz and 48.2GHz AlGaN/GaN HFET devices. More signal distributed effects due to the rails appears in the edge-fed devices over the center-fed devices and in the high frequency devices over the low frequency devices. For a 10dB constant gain, the optimal devices with the maximum peripheries are obtained for each devices and their P1dBmax's and PAEmax's are compared. The optimal device with the largest periphery exhibits the largest P1dBmax and the optimal device with the smallest rail length exhibits the largest PAEmax.; Several layouts---corporate tree, tapered edge, lateral corporate tree (LC), LC with bypasses (LCB)---are designed to improve the center-fed and edge-fed layouts. The methodology used to design the transistor layouts is presented and the device performances are compared. Corporate tree and LCB layouts provide improved signal distribution along the rails of the center-fed layout thanks to synchronized phase delay over the rails and are consequently found to be the optimal layouts.