| Clock signals are commonly distributed globally using either tree- or grid-based networks, requiring many stages of buffering and consuming a large percentage of system power. Many levels of buffering leave the system vulnerable to process, temperature and supply-voltage variability. In large-scale chips, such as microprocessors, active de-skewing approaches have become increasingly popular to contend with static variability, but increase clock latency, making the clock network more sensitive to supply noise and degrading jitter performance.;Resonant clock techniques, in which the clock capacitance is rendered resonant around the target clock frequency by a set of on-chip inductors, addresses many of the challenges associated with standard tree- or grid-based networks. Power-supply-noise-induced jitter is significantly reduced and power savings can be realized in driving the global clock. Despite the advantages demonstrated with earlier prototype designs, resonant systems are still vulnerable to cross-chip variability and transient loading changes.;In this dissertation, an adaptive resonant clock system is introduced based on an injection-locked distributed differential oscillator. In an effort to increase scalability, an active de-skewing system is incorporated in the clock distribution. Due to the filtering properties of injection locking, it is possible to incorporate a de-skewing system into resonant clock networks without significantly affecting jitter performance. In addition, a power management system, in the form of automatic amplitude control (AAC), is also included to further enhance power performance. The AAC system is designed to bias the system to run at a given steady-state clock amplitude with minimal power. A prototype system is constructed using a 0.18mum technology that incorporates on-chip jitter and skew measurement circuits. |
