Strain effects on the performance of silicon MOSFETs

Since the first integrated circuits were invented in the 1960s, semiconductor technology has been so successful to exponentially improve the microprocessor performance during the past half century. This amazing growth becomes more difficult as physical limits of materials are being challenged. Strain technology is a key element in current 32nm node and is widely believed to be used in the future 28 and 22nm technology, since the technique is compatible with other new device structures such as high-k/metal gate, SOI, and FinFETs to deliver large drive current. In this dissertation, strain induced gate leakage current change, mobility enhancement at low temperature, effective work function change are comprehensively studied which could provide a better understanding of the strain technology and its potential application for the most advanced semiconductor devices.;A simple physical picture for stress altered gate direct tunneling current in n and p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) is presented. It is shown that the gate electron tunneling current decreases (increases) for uniaxial tensile (compressive) stress. The stress altered gate hole tunneling current is opposite to the electron current. These results can be understood from the strain-altered out-of-plane effective mass, energy splitting, and carrier population. It is indicated that longitudinal uniaxial tensile stress increases the carrier population in the Delta2 valley having a large out-of-plane mass which results in a decreased electron tunneling current. Whereas, uniaxial tension enlarges the hole gate direct tunneling current by decreasing the density of holes from top band with a larger out-of-plane mass. However, due to weak confinement in accumulation, the normalized leakage current change is higher in accumulation than in inversion. A self-consistent solution to the Poisson and Schrodinger's equation considering the strain Hamiltonian combined with the transfer matrix method are used for modeling the tunneling process.;Hole and electron mobility is studied for strained p-channel and n-channel MOSFETs at low temperature. Longitudinal compressive stress increased hole mobility enhancement is observed as temperature is lowed from 300K to 87K. With a six band k·p model and finite difference formalism, comparison with calculation suggests hole mobility is phonon-limited at room temperatures, while it is limited by both surface roughness and phonon scattering around 87K. Strain induced mobility enhancement at low temperature arises from the reduction of the average hole conductive effective mass due to band warping. However, surface roughness reduction is the dominant physical mechanism for n-channel MOSFETs. Several physical models are discussed and a reasonable modification of present model is presented.;Metal gate induced effective work function change provide a good candidate for work function tuning which is one of the most challenge parts for the present high-k/metal gate devices. Both external mechanical stress and process induced large stress indicated that the effective work function always decrease with the applied stresses regardless the type of stresses. Although the stress induced by the TiN gate strongly depends on the thermal treatment, thermal annealing process constantly generates tension inside the gate. Bowing technique and charge pumping method are used for stress and interface state measurement, respectively. It is indicated that the EWF decrease with the reduction of metal gate thickness and the interface states increase induced donor-like charge generation is the dominant physical mechanism. (Full text of this dissertation may be available via the University of Florida Libraries web site. Please check http://www.uflib.ufl.edu/etd.html)...