Energy scalabilty of the mesh architecture multiprocessor system-on-chip

This dissertation introduces the energy scalability metric for modeling the energy consumption behavior of a parallel processor as the system scales to larger sizes. When developing a parallel processor, the energy consumption properties of the system need to be considered to ensure proper operation. Low-level simulation (gate level, or transistor level) of individual VLSI processing elements can require hours, or even days, to complete. Full simulation of a parallel processor can prove to be intractable without the energy scalability modeling methodology, because the system is potentially orders of magnitude larger.;The mesh architecture multiprocessor system-on-chip (MAMPSoC) is defined, then its energy consumption properties as it scales in size are analyzed in terms of energy scalability. Multicore processors can integrate into multichip parallel processors, yet this design style presents a challenge because the interconnection network between the processing elements is heterogeneous. The MAMPSoC which can be characterized as a mesh-of-mesh network-on-chip (NoC) processors, is an example of the multicore, multichip systems that have become commonplace.;The primary contributions of this dissertation are as follows: (1) introducing the energy scalability and power-delay scalability metrics for parallel system implementation. (2) deriving upper and lower bounds on energy scalability using power-delay scalability. (3) exploring mesh architecture multiprocessor system-on-chip (MAMPSoC) power consumption and timing properties. (4) demonstrating the usage of energy scalability and power-delay scalability in the VLSI design of a MAMPSoC system.;While this study of energy scalability focuses primarily on 1VIAMPSoC systems, the metric is defined to be general enough to apply to any kind of parallel processor. This dissertation provides a roadmap for designing with energy scalability in general systems.