Efficient memory hierarchy designs for chip multiprocessor and network processors

There is a growing performance gap between the processor and the main memory. Memory hierarchy is introduced to bridge the gap for both general propose processors and the specific processors such as network processors. One major issue about the multiple-level memory system is that is needed to be efficiently managed so that the hardware resource is well utilized. In this dissertation, we study three efficient memory hierarchy designs.;The first work is a space-efficient design for CMP cache coherence directories, named Alt-Home to alleviate the hot-home conflict. For any cached blocks, the coherence information can be either stored at one of two possible homes, decided by two hashing functions. We observe that the Alt-Home approach can reduce of 30-50% of the L2 miss per instruction compared to the original single-home approaches when the coherence directory space is limited.;The second work is the greedy prefix cache for trie-based network processor, which can use the cache more efficiently. A sub-tree (both the parent and leaf prefixes) can be cached in our greedy prefix cache so that the cache space can be better utilized.;The results shows the greedy cache has up to 8% improvement on the prefix cache miss ratio compared to the best existing approaches.;The third work focuses on the bandwidth efficient network processors. The hash-based network processor needs to access the hash table to get the routing information. The hash functions needs to be very balanced so that the memory bandwidth can be fully utilized. We proposed three new hash functions based on a small on-chip memory which is available in modern architectures. All of our new approaches can achieve the routing throughput over 250 millions packets per second. Our approaches can also be widely applied to other applications involving information storage and retrieval.