Fabrication and characterization of gallium arsenide MOSFETs and thermography of silicon carbide Schottky diodes

A dielectric stack consisting of gadolinium gallium oxide and gallium oxide (GGO) has previously been shown to result in an unpinned Fermi level on gallium arsenide (GaAs) surfaces, satisfying a key criterion for qualification as gate dielectric. Fabrication of devices to demonstrate the electrical performance of metal oxide semiconductor field-effect transistors (MOSFETs) incorporating an epitaxial layer structure similar to that of a pseudomorphic high electron mobility transistor and GGO as the gate oxide is the subject of the first portion of this work. The most challenging process step was the formation of reliable source and drain ohmic contacts. Though enhancement mode device operation was demonstrated, the use of ion milling to etch GGO, combined with the sensitivity of the device structure to the aluminum nitride dielectric cap layer, resulted in devices that degraded with time. Replacing the aluminum nitride cap layer with silicon nitride and using dilute hydrochloric acid to etch the GGO improved the stability of the ohmic contacts considerably. Devices fabricated using the new process were used to assess the high frequency performance of the GaAs MOSFET device structure. Transconductance values of about 180 milli-siemens per millimeter of gate width, a cutoff frequency of 14 gigahertz and a maximum oscillation frequency of 48 gigahertz were measured on devices with gate lengths of 0.8 microns. A small signal model was extracted for the GaAs MOSFET. Under large signal conditions and class A bias, a power added efficiency of 38 percent, a power gain of 13 decibels and a maximum output power of 31 milliwatts per millimeter of gate width were measured. Pulsed current-voltage characteristics showed dispersion, suggesting the presence of traps either in the oxide or at the oxide-semiconductor interface.The second part of this work is related to nonideal forward current characteristics observed at low forward voltages in silicon carbide (SiC) Schottky barrier diodes (SBD). This nonideality has been attributed to current flow in crystal defect-induced low Schottky barrier height (SBH) patches. The objective of this work was to validate this theory by thermally imaging the excess power dissipated in the low SBH patches Infrared and liquid crystal thermography techniques were used to attempt spatial mapping of the power dissipated in the low SBH defect regions. Hot spots were not observed. Tung's model for the currents through SBDs with inhomogenous SBHs was used to explain the absence of hot spots in the thermography results.