Compiler optimization for translating software binaries onto FPGAs

Applications that require digital signal processing (DSP) functions are typically mapped onto general purpose DSP processors. The FREEDOM compiler has been developed to automatically translate software binary codes targeted for general DSP processors into Register Transfer Level VHDL or Verilog code to be mapped onto commercial FPGAs. This dissertation describes numerous compiler optimizations to translate software binaries to hardware.;We describe novel algorithms for pipelining software loops considering the circular dependency and memory life-time holes from software binaries for efficient hardware implementation. We develop sophisticated algorithms for converting sequential algorithms into streaming algorithms. We create a set of stream descriptors to describe the stream patterns from ordinary programs. The stream operations are introduced to compare the streaming relationship between producer-consumer kernels. The hierarchical algorithm identifies the streaming relationships and constructs streaming architectures.;We evaluate our algorithms on complex DSP and communication benchmarks. Results indicate speedups of 1.4x for the software pipelining over the non-pipelined design, and speedups of 1.2x--8x for the streaming architectures over the non-streaming ones. The experimental results show that the software pipelining and streaming algorithms presented in this dissertation are efficient methods for improving the parallelism in the binary-to-hardware translation.