Study And Design On Multi-mode Multi-standard RF Transmitter Based On Delta Sigma Modulator

Wireless communication system is in evolution,new and old systems exist at the same time,and there will be kinds of wireless communication system on the same terminal for different application scenarios.Integrating multiple wireless transceivers on one chip is a way to save circuit area and reduce cost.A reconfigurable wireless transceiver is valuable.A Delta Sigma Modulator(DSM)based transmitter is a kind of reconfigurable transmitters to meet variety of wireless communication standards.It consists of a DSM and a switched power amplifier.In addition to the power amplifier,DSM is completely processed in the digital domain.It is a kind of transmitter close to SDR architecture and has reconfigurable characteristics.This dissertation studies the DSM based transmitter.The main contents and innovation points are as follows.Firstly,the basis of the DSM based transmitter is studied.This part mainly studies the signal-to-noise ratio(SNR)of low-pass and band-pass DSM,the structures and their advantages and disadvantages of the existing DSM bsed transmitters,the evaluation parameters of the transmitters and the digital up-convertor in the transmitters.The SNR for BP-DSM is lower than the LP-DSM under the same order and oversampling ratio.The LP-DSM based transmitter has several advantages over other DSM based transmitters.The digital up-convertor in the LP-DSM based transmitter is discussed.One of the innovations of this dissertation is proposing an 8-1 multiplexer based digital up-convertor,which reduces the clock frequency of the traditional 4-1 multiplexer based digital up-convertor by 1/3.Secondly,a multi-bit DSM based transmitter architecture and a tunable DSM based transmitter are proposed.DSM based transmitter mainly includes in-band signal-to-noise ratio(SNR)and coding efficiency.In-band SNR determines the signal quality of transmitter output.The coding efficiency determines the ratio of useful signals in the transmitter band to the output power of the power amplifier.The signal-to-noise ratio of a DSM transmitter is determined by the order of the DSM,the oversampling rate and the number of output bits.Under certain SNR requirements,tradeoffs can be made between order,oversampling rate and output bit number.The second innovation point of this dissertation is the multi-bit DSM based transmitter.Multi-bit output not only reduces quantization noise,improves signal-to-noise ratio,but also improves coding efficiency.The structure and components of multi-bit DSM based transmitter are given,including multi-bit DSM,multi-bit digital up-mixer and multi-bit power amplifier.The multi-bit transmitter is simulated by using the OFDM signal of peak-to-average power ratio(PAPR).The local oscillation frequency of traditional DSM-based transmitter is limited by the sampling frequency of integer multiple DSM.A transmitter architecture based on tunable error feedback DSM(EF-DSM)structure is proposed to achieve arbitrary frequency coverage.This is the third innovation point of this dissertation.An improved tuning EF-DSM is presented and verified by using FPGA.Thirdly,two methods are proposed to improve the processing speed of DSM transmitter.The first method is a bus-splitting structure to reduce the long word length of adder which restricts the processing speed of DSM to several short word length processing.This not only improves the processing speed,but also saves hardware resources.A multi-bit EF-DSM transmitter architecture based on bus-splitting is proposed,which improves the signal processing speed by 39% to meet the requirement of signal-to-noise ratio.This is the Fourth innovation point in this dissertation.The second method is an improved time interleaving EF-DSM(ITI-EF-DSM).Time interleaved EF-DSM based on direct transform will face the problem of increasing critical path delay.Because DSM is a feedback system,improperly adding pipeline will destroy the result of signal processing.An ITI-EF-DSM is adopted to overcome the shortcomings of the direct time interleaving method,so as to achieve required signal processing speed.This is the Fifth innovation point in this dissertation.The two improved DSM transmitters have been verified on FPGA.Fourthly,the class E power amplifier(PA)in DSM transmitter is studied,and a new type of inverse class E power amplifier is proposed.Switched power amplifier is another key module of DSM-based transmitter.The final efficiency of power amplifier is affected by the duty cycle of driving signal of DSM transmitter.Class E PA has the advantages of high frequency and high efficiency.This dissertation summarizes three known amplifiers: traditional series filtered class E,inverse parallel filtered class E and parallel filtered class E.The influence of duty cycle of driving signal on the efficiency of class E PA is studied in detail.A novel inverse class E PA with series filter is proposed,which is the sixth innovation point.The principles of series filter inverse class E PA are analyzed theoretically.And the efficiency for drive signal duty cycle deviation from 50% is analyzed and simulated.