The Study On The Design And Key Process Of Advanced 4H-SiC VDMOSFETs

As a typical representative of the third-generation semiconductor materials,silicon carbide?SiC?has superior material properties?such as high breakdown electric field,high thermal conductivity,high electron saturation speed,and strong radiation resistance?compared with the previous two generations of semiconductor materials,which is more suitable for making high temperature,high frequency,radiation resistant power devices.In recent years,with the development of power device applications,silicon-based devices could not meet higher performance requirements according to high voltage,high conversion efficiency and power density due to the limitations of thematerial,thus making the third generation semiconductors including SiC are optimum choices for replacing Si-based material.As an important power device,SiC power MOSFET is gradually applied in power electronic systems due to its simple gate drive circuit,high operating frequency,high power density and high conversion efficiency.Although the researchs on 4H-SiC MOSFET have made remarkable progress in recent years,there are still some issues to restrict the performance of4H-SiC MOSFETs for further improvement,such as SiO₂/SiC interface quality,gate voltage stability,high reliability terminal structure design,high reliability ohmic contact preparation process and higher performance design.Based on the problems mentioned above,this dissertation focuses on the following four aspects of theoretical and experimental research.The main research contents and innovations are as follows:1)Research on high mobility,high reliability gate oxide process.The experiment of NO/O₂/NO sandwich nitrogen annealing process was designed,by which the 4H-SiC VDMOSFET flow film experiment was carried out.The results show that the interface state near the conduction band at the interface of the oxide layer is reduced to 2×10¹² eV^-1cm^-2,the breakdown field strength of the gate oxide layer is 9.5 MV/cm,and the maximum field effect mobility of the lateral n-MOSFET device is reached 36 cm²/Vs,which is close to the peak level of the reported result utilizing nitriding annealing process.The NBTI characteristic test was performed on the fabricated P-type capacitor and the lateral n-MOSFET device.Compared with the nitriding annealing process in the literature,improvements in NBTI characteristics indicate that the process is feasible in device fabrication.2)Research on low temperature ohmic contact.Due to the particular structure of the4H-SiC VDMOSFET device,high ohmic contact annealing temperatures can cause degradation of the device gate oxide.Hence,a process study on simultaneous formation of N and P ohmic contacts at low annealing temperatures was developed for SiC MOS devices.Based on the formation mechanism of SiC ohmic contact and the process realization method in the fabrication process of VDMOSFET device,a metal scheme of Ni/Ti/Al/W was proposed.A highly doped region is formed by ion implantation on the n-type epitaxial wafer,and a Ni/Ti/Al/W?80/30/110/50 nm?metal combination is used to form an N-and P-type ohmic contact at a low temperature of 750°C.The specific contact resistance of N-type ohmic contact is 8×10^-4?·cm²,and the P-type ohmic is 4.1×10^-5?·cm².The annealing temperature is the lowest value of the n-type and p-type ohmic contacts formed by the rapid thermal annealing process reported in the literature,which satisfies the preparation requirements of the SiC MOS device.The ohmic contact samples of Ni/Ti/Al/W were tested and analyzed by SEM,XRD,AES and TEM.It is found that the introduction of W element is the reason why Ni/Ti/Al/W can form an ohmic contact at a low temperature.3)Studies on P-well FLRs termination using low dose ion implantation with low damage and high-reliability.Based on the working principle and design method of the traditional P+FLRS terminal structure,a new P-well FLRS terminal structure suitable for4H-SiC VDMOSFET devices is proposed and designed.P-well ion implantation parameters is used to form a field limiting ring,avoiding high Dose P+implanted damages in the surface of the termination region.The P-well ion implantation concentration of the key parameters in the P-well field-limiting terminal structure was designed,and the 1200 V non-uniform P-well field-limited ring structure was simulated.Then the device using the terminal structure was processed.The results show that the near-interface traps of P-well and P+samples are8.24×10¹¹ cm^-2 and 3.39×10¹² cm^-2,respectively,which indicates that better SiO₂/SiC interface quality in the terminal region can be obtained.And the device with P-well FLRs termination structure has a breakdown voltage of 1610 V,which is 90%of the breakdown voltage of ideal parallel plane junction.Finally,the breakdown voltage temperature test of the VDMOSFET device using this termination structure is carried out.The results show that the P-well FLRs structure still meets the breakdown requirements at high temperatures.4)Research on high threshold 4H-SiC power VDMOSFET devices.Based on the requirements for high threshold power MOSFET application and device theory basis,device structure parameters related to on-resistance,threshold voltage,breakdown voltage and structural capacitance are optimized.Combined with the results of process optimization in the previous chapters,a high performance 1200 V 40 A 4H-SiC power VDMOSFET device with a threshold voltage of 4.1V was designed by optimizing the P-well ion implantation design and reducing the cell size.The measurements show that device linear region resistance is 80 m?at the gate voltage of 20 V,the on-state current can reach 40 A at the drain-source voltage V_DS of 3.2 V,the threshold voltage of the device is 4.1 V and the breakdown voltage is 1620 V,which is firstly reported in China.Finally,threshold voltage reliability testing was performed for 1200 V 40 A VDMOSFET devices,including the dependence of threshold voltage on temperature stress and bias voltage stress.Compared with similar products in demestic and abroad,it is found that the threshold voltage of the device is always larger than 3 V,indicating that the high threshold voltage 4H-SiC VDMOSFET device is suitable for the applications in high temperature and high frequency devices.