Research Of Data-driven Reconfigurable Array Processor Architecture

Although the traditional processor architecture has high flexibility,it is difficult to meet the increasing efficiency demand of diversity application.Application specific integrated circuit has fast execution speed and low power consumption,but it lacks enough flexibility to meet the requirements of emerging and evolving applications.The reconfigurable architecture combines the characteristics of products' standardization and applications' customization,computation efficiency and programming flexibility,so it is the development direction of future processor architecture.In post Moore era,the wire/inconnect delay has much more greater than the gate delay,which has become the main bottleneck restricting the further improvement of chip working frequency.To avoid long interconnection and reduce the power consumption of the system,the computer architecture presents the trend of localization,regularization and simplification.Processor design has also experienced the development process from the complexity of single core to the simplification of multiple core.A reconfigurable array processor that is composed of a large number of simple processing cores connected by two-dimensional adjacent short line is exactly in line with the development trend of the architecture.Therefore,it is of great significance to study data driven reconfigurable array processor.In order to improve the performance of reconfigurable computing,this paper mainly studies data driven reconfigurable array processor architecture,and data driven dynamically reconfigurable array structure,data driven reconfigurable array processor,distributed shared memory structure based on unified addressing,and dynamic self-reconfiguration mechanism,aiming to maximize task parallelism,improve the flexibility of data driven dynamically reconfigurable arrays,alleviate the increasingly serious problem of "memory wall",reduce the latency of algorithm switching and improve computing resources utilization.The main contents of this paper are described as follows:(1)In order to maximize the task parallelism and improve the computing performance of reconfigurable architecture,this paper first studies the dynamic reconfigurable array structure which adapts to the data flow application,and then presents a data driven reconfigurable array structure.In order to further maximize task parallelism and improve resource utilization,two other types of data driven reconfigurable array structures are proposed.Meanwhile,two kinds of configuration information network are studied: bus structure and H-tree network structure.In order to fully analyze the performance of the proposed three kinds of structure,parts of data flow application algorithms are mapped.Performance statistics are done according to simulation results,and the statistical results show that the proposed array can accommodate the data flow diagrams effectively.At the same time,it is able to complete data transfer between adjacent processing units in one cycle because of employing data driven adjacent interconnection interface.The whole processing is similar to pipeline structure,so the throughput reaches to one clock cycle and it has higher computing efficiency.(2)In a single task mapping,data driven reconfigurable array structures that support fixed configuration or a small number of multi-operation configurations are lack of flexibility.In order to further improve the flexibility of structure and meet the mapping requirements of more complex applications,this paper attempts to use software programming to realize the reconfiguration of array functions.Two kinds of adjacent interconnection interface circuit are proposed: single buffering and double buffering.Meanwhile,in order to accelerate transcendental function computing which is crucial in some applications,we design a four-way parallel pipeline structure of transcendental function accelerator,and a kind of adjust intercept piecewise linear approximation algorithm is proposed to simplify the calculation process.Some image processing algorithms and AlexNet convolutional neural network are mapped on proposed architecture in this paper.Performance statistics are done according to simulation results,and the statistical results show that proposed double-buffered adjacent interconnection interface circuit can complete data transfer between adjacent processing elements within one clock cycle,greatly reducing the data transfer delay between adjacent processing elements.The average error of transcendental function accelerator is about 0.01%.The throughput of most functions is up to one clock cycle,and the calculation delay is 2~7 clock cycles.The proposed data driven reconfigurable array processor can perform a variety of computing tasks.(3)To ease the problem of "memory wall" in data driven reconfigurable array processor,this paper proposes a distributed shared memory structure based on unified addressing.Global distributed memory banks are connected effectively by two level interconnection structure which is local cross-interconnection and global NoC interconnection.Meanwhile,local cross-interconnection is further studied,and three kinds of high speed switching structure are proposed.This paper also develops a simulation platform with graphical interface,and develops a variety of test cases on the platform.The function verification and performance statistics of proposed distributed shared memory structure are also done on the platform.In terms of access bandwidth,the remote access is 0.15GB/s and the local data access is 6.4GB /s.In terms of access latency,local data access latency is only 1~2 clock cycles,and remote access latency is about 11~18 clock cycles.The experimental results show that the proposed structure has higher memory access bandwidth and lower local data access latency.Finally,in order to reduce the latency of algorithm switching and improve the resource utilization,this paper studies the reconfiguration mechanism of software programming to realize the reconfiguration of hardwire functionality,and then proposes a dynamic self-reconfiguration mechanism of "data driven + configuration driven" dual-drive,which effectively realizes the self-reconfiguration of PE.Meanwhile,a variety of data-intensive applications are mapped on it and the performance of proposed mechanism is analyzed and compared based on simulation results.The experimental results show that the proposed self-reconfiguration mechanism can effectively reduce the configuration information and have lower processing time.