Research On Key Technologies For Efficient Routing Of Network-on-chip

With the shrinking of transistor sizes,more intellectual property(IP)cores are being integrated onto a single chip to implement more complicated system functions.In traditional System-on-Chip(SoC),the CPU core and the other IPs are interconnected by bus.As the number of IP cores continue to scale in SoCs,the architecture of bus-based communication has become the performance bottleneck of system due to the growing of bandwidth requirement and non-predictable wire latency.Solution to address the communication demands of future systems,Network-on-Chip(NoC)based on computer network has become an emerging solution due to its reusability,scalability,and parallelism in communication infrastructure.The routing policy is one of the most important considerations in NoC design,which has an important impact on network performance and power consumption etc.In this work,the reported routing strategies are analyzed.The deterministic routing algorithms suffer from a poor performance with a low complexity,while the adaptive routing algorithms provide an improved performance with a high complexity.To achieve efficient routing,the router architecture and algorithm are optimized for a high routing performance and a low overhead.The load balancing routing techniques,bufferless routing and adaptive routing based on Software-Defined-Network-on-Chip(SDNoC)are studied mainly.The contributions in this thesis are as follows:(1)In the research of load balancing routing,a load balancing routing aggregation design is proposed.The computing nodes with specific latency required and dense traffic and long distance in network are gathered into the same routing node to form an aggregation router.To improve the overall performance,a load balancing routing algorithm for aggregation router is presented.To reduce implementation overhead further,a low overhead load balancing routing is proposed.In this scheme,a balance toggle identifier is employed to select a suitable initial direction for the injected packet.Afterwards,the packets are routed according to XY or YX routing along the initial routing direction of X or Y in the network.Once output ports contention arise,the heavier-first scheme is used to address,which means that the routing direction with a heavier routing load has a higher priority to get the desired output port.Experimental results show that the proposed load balancing schemes yield an improvement of routing performance in latency with a less hardware overhead compared with the reported adaptive routing schemes.(2)In the research of bufferless routing,a load balancing bufferless deflection routing is proposed.In this scheme,the processing within router can be implemented in a single cycle due to the simplified router architecture and the optimized pipeline.The load balancing injection strategy is employed as well for a suitable initial direction.Once output ports contention arises,a nearer and deflected first priority policy is used to address contention.In details,the deflected flit has the highest priority to provide a guarantee of livelock freedom.When the undeflected flits contend the same output ports,nearer to destination router get the desired output port to reduce network load.To provide a reliable traffic on chip,a fault-tolerant deflection routing is proposed.The faults on links and routing channels are diagnosed by cyclic redundancy check(CRC)and the backup links and a redundant fault-tolerant unit at router-level are employed to sustain the traffic reliability in NoC.Once the faults on links or routing channels are acknowledged,the retransmitting flits are used for fault-tolerant.For the bufferless deflection routing,the priority policy of nearer and deflected first is employed to improve routing performance as well.Experimental results show that the proposed load balancing bufferless deflection routing can enhance performance with a low hardware overhead,the proposed fault-tolerant routing scheme can ensure the reliability of traffic in NoC with a slight increase of hardware overhead.(3)In the research of software defined network on chip(SDNoC),a fully adaptive routing is proposed based on SDNoC architecture.The proposed fully adaptive routing scheme leverages the hierarchical design of SDNoC to decouple path determination from routing forwarding.The fully adaptive routing path is determined by software techniques in the control layer of SDNoC to select the least load adaptive path within the region of the given source-destination pair,which maintains flexibility of routing strategy and reduces hardware overhead.The determined path is encapsulated into the packet to guide the forwarding.To reduce deflection of bufferless routing based on SDNoC,a zero deflection bufferless adaptive routing is proposed.The least congested path is selected by software of control layer in SDNoC as well.Furthermore,a mechanism of the delayed configuration dispatch and dropped packet is employed to avoid deflection.Experimental results show that the proposed routing schemes can reduce the traffic latency at a high injection rate due to the latency of software.The hardware overhead is reduced for the elimination of routing selection logic from the conventional router.