320×256 LW IRFPA ROIC With High Dynamic Range

Long wave infrared detector is an important direction for the development of the third generation infrared detector.The infrared focal plane array consists of two parts: a photodetector array and a readout circuit.Long wave infrared background and target radiation signal is strong,it is necessary to design a high charge storage capacity readout circuit to achieve high dynamic range and improve the temperature resolution of target detection.Due to the large dark current and high background,the dynamic range of the readout circuit directly affects the detection performance of the system.The readout circuit is an integral part of the infrared focal plane,which is used to integrate and amplify the infrared signal and transmit the signal from the parallel detector to the serial output.The circuit structure with high readout efficiency and high dynamic range is the technical difficulty of the long wave infrared focal plane readout circuit.This paper focuses on the design of long range infrared focal plane readout circuit with high dynamic range and analyzes the difficulties in the design of long wave infrared readout circuit with high dynamic range.According to the characteristics of long wavelength infrared detector dynamic node impedance is too low,dark current is large,the background is high,I designed a capacitor feedback transimpedance amplifier(CTIA),high dynamic range long wave infrared focal plane readout circuit structure in the finite element area of 30?m pixel area array focal plane.The innovative use of time-sharing sharing capacitance structure,the use of CTIA structure,30?m center distance,the unit maximum effective charge capacity is 57.5Me~-.This paper introduces the design of 320×256 readout circuit and the design and simulation of the readout circuit structure,signal sampling and output stage.The readout structure of the circuit is CTIA,and the performance of CTIA is theoretically deduced and verified by simulation.In the design of the digital circuit module,the circuit uses the rolling readout mode,and designs the internal working sequence,which solves the problem of the frame rate reduction caused by the time integration.The circuit front-end simulation,back-end simulation is completed in layout design based on CSMC 0.35?m standard CMOS process,and tape out.The 320×256 readout circuit has been tested at room temperature and low temperature,the circuit power consumption is 208 mW,the linearity is 98.9%,the readout rate is 2.41 MHz and the charge capacity is 49.1Me~-,the circuit has reached the design requirements.