Study Of Design And Simulation Techonoly For Silicon-based Strained MOS Devices

Silicon devices play a decisive role in the semiconductor industry. Scaling downthe feature size has been the main method of moving silicon device’s performance.However, as the device is scaled down to the nanometer scale, serious challenges areposed by the material properties, device physics and fabrication technologies. Suchchallenges have impelled researchers to find for various alternatives and as a result,Silicon-based strain technology has emerged. By inducing stress into Si, the carriermobility can be enhanced and the I-V characteristics of MOSFET based on thistechnology can be improved. Therefore, Silicon-based strain technology is regarded asan important method to extend the Moore Law in the next two decades. Thisdissertation is mainly concerned with the manufacture of strained materials, design andsimulation of strained MOSFET. The author’s major contributions are outlined asfollows:1. The formation mechanism and behaviors of treading dislocation defect inSilicon-based strained and relaxed materials are systematically investigated in thisdissertation, then a new method to improve the quality of strained materials has beendemonstrated, combining the low temperature technology with compositionally gradedSiGe technology. The growth experiments are investigated by RPCVD. Thecharacteristics of the materials are checked by AFM, TEM and Raman Spectra. Theresults show that treading dislocation density is lower than105cm-2，proving excellentelectronic and structural properties of this new material structure.2. The carrier transport mechanism along the vertical direction in strained-Sin/pMOS and strained-SiGe pMOS structures have been studied, then the formationmechanism of “Plateau” observed in the C-V characteristics of strained-Si n/pMOS andstrained-SiGe pMOS structures has been explained. Physically based analytical modelsfor their C-V characteristics were developed and solved to predict the performance ofthe “Plateau” in these structures, and the dependence of the “Plateau” on dopingconcentration was analyzed.3. In order to suppress the impaction of “Plateau” on strained-Si and strained-SiGepMOSFETs, the conditions for strong inversion of these devices has been studied, andthen the models of flatband voltages and threshold voltages have been established, bysolving the Possion`s equation. To improve the performance of strained-Si nMOSFET, the polity-Si gate on the top of strained-Si nMOSFET has been substituted byhetero-poly SiGe gate, showing advantages of both “Gate engineering” and “Strainengineering”. The threshold voltage of this new device is analyzed by physicallyderiving the models of the threshold voltage.4. Basing on the materials and models studied in the previous section, design ofstructure physical parameters, layout, and process for strained Si nMOSFET andstrained SiGe pMOSFET are carried out, then several groups of strained devices weremanufactured. The tests of the devices taped out show that Si-based Strain MOSFEThas more improvement than conventional Si MOSFETs. Also, the electrical data usedfor parameter extraction were obtained.5. Since the performance and models of Silicon-based strained MOSFET aredifferent with that of bulk Si MOSFET, the parameter extraction technology for bulk SiMOSFET can not service for strained device well. So the technology of parameterextraction for Silicon-based strained MOSFET has been studied. With the help of VC++programming language, the software for extracting the parameter of strained-Si,strained-SiGe MOSFETs SSMPE has been developed finally.6. To verify the extraction results of software SSMPE, the equivalent circuitmodels of strained-Si and strained-SiGe MOSFET has been established, then plug-inpackage for EDA simulation has been developed with Verilog_A, which can be used inSpice/Spectra simulator, achieving the simulation of silicon-based strain MOSFETsuccessfully.