Research On The Power Analysis Resistant Technology Of Cryptographic IC

As the cornerstone of information security, the cryptographic IC represented by the smart card chip plays an important role in many industries. Different from the traditional crypto analysis, differential power analysis as a kind of side channel analysis, more focuses on the concrete implementation of cryptographic algorithm. Differential power analysis (DPA) conducts the attack by means of the correlation between power consumption and data processed by the encryption circuit. It has posed a severe threat to the cryptographic IC, and aroused great concern from the relevant researches at home and abroad. Against this background, the analysis of potential threat of cryptographic IC and the exploration of the effective countermeasure will be of great importance to the protection of the information system security.This thesis first presented an overview of the DPA theory, and then generalized the general design flow for the cryptographic ICs against DPA. The thesis also set up the power analysis research platform oriented to different design stages and countermeasures. In addition, the evaluation method of the DPA resistant capability was also discussed. On these bases, the thesis carried out the research about power analysis technology and multi-level countermeasures.In the aspect of power analysis technology, in case of Piccolo, this thesis proposed a kind of the ciphertext based DPAattack model oriented to the parallel implementation of Piccolo algorithm. This model employed the idea of “divide and conquer” and utilized the partial correlation theory between power consumption and data. The model lowered the computation complexity to (2×220+2×212+216) from the280oriented to the mathematical analysis, and made possible disclosing the secrete key. The effectiveness of this model was verified based on the FPGA research platform. The successful recovery of the80bit primary key showed that Piccolo is vulnerable to DPA attack.In the aspect of algorithm-level countermeasure, this thesis proposed an improved exhaustive search algorithm for area-optimal quadratic decomposition of4×4S-box threshold (3,3) sharing implementation. With the algorithm, the target search space can be reduced to1/(4!) of existing algorithms. On this basis, in view of the application to the resource-constrained and security-sensitive field, the thesis proposed a secured Piccolo implementation scheme and gave a solution to the potential glitches risk by the clock-controlled latch. With Chartered0.18μm process and100kHz operating frequency of RFID, the scheme proposed by this thesis occupies only2155GE with the average current of approximately2.60μA. The scheme can resist the DPA attack based on at least100000groups of samples, satisfy the extremely small areas and low power consumption, be suitable for the RFID-tag chip in security-sensitive field.In the aspect of circuit-level countermeasure, in order to eliminate the early propagation effects(EPE) which lie in traditional dual-rail precharge(DRP) logic and obtain the relatively small area overhead, the thesis proposed a new DRP logic—Differential Pass-transistor Precharge Logic (DP2L) based on the in-depth analysis of the complementary pass-transistor logic(CPL). The DP2L solved the problem of EPE effectively while making the power consumption of the basic logic unit constant, close to the area overhead of WDDL-type cryptographic application circuit. The DPA results based on SPICE simulated power consumption data showed that the DP2L was about20times of the DPA resistant capability of the WDDL in the principle of average determination and under the condition of the equivalent noises. The resource consumption, power constancy and DPA resistant capability of DP2L were evaluated by a kind of simplified circuit model proposed by this thesis. According to the evaluation result, the model circuit implemented by DP2L occupied86%of the area overhead of the WDDL, with power constancy and DPA resistant capability significantly superior to WDDL.In the aspect of system-level countermeasure, to improve the robustness of the current flattening circuit based on the current detecting scheme by resistor, this thesis proposed a current flattening circuit scheme based on variable reference voltage. This circuit scheme can be self-adaptive to the supply voltage, and reduce the risk in the compensation circuit failure caused by the fact that the actual supply voltage can be lower than the designed voltage. Besides, the scheme was not sensitive to the resistor process deviations, which can reduce the additional design margin due to such deviations and lowered the power consumption of the whole cryptographic ICs. With Chartered0.18μm mixed-signal CMOS process, a circuit suitable for smart card chip with0-8mA working current was implemented based on the scheme. The circuit’s core layout area was about12.7×103μm2. With actual current traces of a MCU as SPICE simulation stimulus, this thesis analyzed the flattening effectiveness and DPA result. According to the SPICE simulation analysis result, this circuit can gain98.7%current attenuation of AC RMS current and significantly improve the original cryptographic IC’s resistance against DPA. In addition, in order to lower the overall power of cryptographic IC with the current flattening countermeasure, this thesis added configurability to the above scheme and proposed a low power current flattening circuit scheme. The scheme can realize the hierarchical control of the flattening current by dynamically changing the current detecting resistor or the reference voltage, reduce the overall power consumption of cryptographic IC. Besides, configurability can also easily fit in cryptographic ICs with different peak currents, and widen the scope of application of the current flattening circuit.