Research On Digital Signal Processor Architecture For Cognitive Radio

With the rapid development of the computer and micro-electronic technologies, thecommunication technology has been changed a lot. The widely used wirelesscommunication technology becomes more and more important in our daily work andlife. However, with the rapidly increasing requirement for faster multimedia wirelesscommunication, the need for more spectrum resources is controdictory to the fixed andlow untilized spectrum allocation policy all around the world. Cognitive radio can beseen as software-defined radio with the capability of spectrum sensing and intellegentdecision. Although the cognitive radio push more requirement for spectrum sensing andreconfiguration computing beyond the software-defined radio, which is really achallenge to software-defined radio processors. The benefit of cognitive radio is quiteobvious, it not only improve the rate of spectrum utilization but also improves theintelligence of communication systems. Thus the relevant research on the digital signalprocessor architecture for cognitive radio is actually very important. This thesis issupported by the National High Technology Research and Development Plans of China(“863” Plan) and a number ofNationalNature Science FundationofChina (NSFC). Thespectrum sensing algorithm and spectrum sensor architecture, the congitive radioreconfigurable baseband processor and the autonomic cognitive radio node architecturehave been investigated. The main research includes the following topics:1、 Cognitive radio blind spectrum sensing algorithms based on energy detectionand the spectrum detectors architecture based on these algorithms. Blind spectrumsensing is very important for cognitive radio system implementation beacuse we assumethe cognitive radio know nothing about the primary user information. For therequirement of computing for energy detection and changable detection precision, areconfigurable pipeline FFT processor is proposed, the FFT processing points vary from64to2048, the area and power consumption of this FFT processor is fairly low. Thetwo stages energy detection algorithm is proposed. Based on the two stages energydetection algorithm and the reconfigurable FFT processor, a detection performanceadjustable energy detector is designed and implemented.2、 Parallelized cyclostationary feature detection algorithm and the parallelcyclostationary feature detector architecture implementation. Cyclostationary featuredetection has been widely used in multiple narrowband signals difference of arrival(DOA) estimation, weak spread-spectrum communication signal identification, andradar signal parameter estimation. But high computational complexity ofcyclostationary feature detection limits its usage as a signal analysis tool. Acomputational efficient parallel cyclostationary feature detection algorithm is proposedand tested on our multicore software-defined radio processor. For a typical spectrum sensing task with32768samples of8MHz spectrum, the spectrum sensing time is78.8ms. The parallel cyclostationary feature detector architecture based on the abovemetioned parallel detection algorithm is implemented. Combined with energy detector,which is easy to be implemented, a reconfigrable energy and cyclostationary featuredetector is proposed. The detection task of this detector can be devided into two stages,the energy detector for first stage coarse-grained sensing and the cyclostationary featuredetector for second stage fine-grained sensing task. The reconfigurable spectrumdetector achieves a balance in the spectrum sensing performance and powerconsumption overhead.3、 Cognitive radio reconfigurable baseband processor architectrue design andimplementation. Cognitive radio reconfigurable baseband processing is a challegingtask for digital signal processor. A cognitive radio baseband processing model isproposed and the NC-OFDM transimission technology based baseband processingcomputing character is analyzed. Cognitive radio put an emphsis on the dynamicreconfigurable, so the reconfigurable architecture model for the baseband processingrequirement is proposed. CORA (Cognitive radio Oriented Reconfigurable basebandArchitecture), a multicore reconfigurable processor architecture based on the model isdesigned. The numerical results show that this architecture is suited for NC-OFDMbased cognitive radio baseband processing with reconfigurable capability.4、 Autonomic cognitive radio concept model, cognitive cycle and autonomiccognitive radio node architecture prototype design and implementation. In order toachieve the evolution from contemporary spectrum sensing cognitive radio to the idealcognitive radio, the autonomic system design principles are investigated and the idealcognitive radio cycle is proved consistent with this principles. The autonomic cognitiveradio conceptual model and the autonomic cognitive radio cycle are proposed, alongwith the formal definition of its different parts and function. Based on the open-sourceautonomic communication platform, ACE Toolkit, the autonomic cognitive radiosimulation environment is implemented. The autonomic cognitive radio architecturemodel is the key step to system realization. ACRA (Autonomic Cognitive RadioArchitecture), an MPSoC (Multiple Processor System-on-Chip) based architecture forautonomic cognitive radio, is proposed. We mapped the cognitive radio capabilitiesdefined in the IEEE802.22standard onto the ACRA, and experiment results show thefeasibility of spectrum management function in ACRA and its enhanced performance inspectrum sensing.In the summary, this thesis has investigated a number of key technologies for thedigital signal processor architecture for cognitive radio. Spectrums sensing coprocessorarchitectures for cognitive radio, cognitive radio baseband processing model andreconfigurable baseband processor and autonomic cognitive radio node architecture have been proposed. This thesis is expected to accelerate the theoretical andimplemental research on cognitive radio.