Low Power Design Techniques For Analog-to-digital Converters In Advanced Digital Process

The integration density, speed and power consumption of the digital circuits arebenefiting from the evolution of the semiconductor fabrication technology and thedevelopment of the modern digital signal processing (DSP) theory. Analog-to-digitalconverter (ADC), as the interface between the analog and the digital signals, is animportant and indispensable component of the integrated circuit (IC). Deepsub-micron digital process is often preferred for system on chip (SOC) with ADCintegrated due to lower cost and higher speed. However, conventional amplifier-basedanalog circuit design techniques have a lot of limitations in advanced digital processand the performance is also compromised due to low supply voltage. In order to solvethis dilemma, this paper introduces a concept called “Technology-Scaling-Friendly”.It requires fully compatibility with advanced digital process, capability of low supplyvoltage operation and high power efficiency.Three low power design techniques for flash ADC are invented according to theproposed concept and their prototypes are implemented:1. One-time time-domain comparator converts the analog input to digital signalby using linear pulse-width-modulation (PWM). After checking the sequenceof the rising edges, the trigger determines which one is larger. The prototypeis a5-bit125MS/s flash ADC in SMIC65nm CMOS process. The simulationresults indicate that the ADC consumes367μW at1.0V supply voltage,occupies0.022mm~2and has only0.02pF input capacitance.2. Digital foreground calibration circuit adjusts the resistor according to thecomparison results so as to decrease the one-time time-domain comparatoroffset and eliminate the comparison threshold non-monotonic due tomismatch error. The calibration works only once after power on and doesn tconsume additional power in normal mode. The prototype is a6-bit125MS/sflash ADC in SMIC65nm CMOS process. The simulation results indicatethat the ADC consumes803μW at1.0V supply voltage, occupies0.083mm~2and has only0.03pF input capacitance.3. Resistor averaging makes use of serial connected unit resistor to balance thePWM array output reference pulses, which has the same function as the digital foreground calibration. Its structure is simple and the static powerconsumption is very low. The prototype is a6-bit40MS/s flash ADC in SMIC65nm CMOS process. The measurement results indicate that the ADCconsumes540μW at1.0V supply voltage and occupies0.1mm~2.Three low power design techniques for successive-approximation-register (SAR)ADC are prototyped based on the proposed concept:1. The D flip-flop of the single-ended time-domain comparator is replaced byRS trigger for the differential configuration. Consequently, a referencevoltage is saved and the operation point can be boosted for higher speed. Theprototype is an8-bit4.35MS/s SAR ADC in SMIC65nm CMOS process. Themeasurement results indicate that the ADC consumes6.6μW at0.6V supplyvoltage and occupies0.011mm~2.2. Separated-capacitor array technique splits the conventional single capacitorarray into two and improves the capacitor switching efficiency by making thecomparison before the switching. By controlling the bulk bias of thedifferential pair with increasing resistance spread resistor ladder, the digitalforeground calibration circuit can reduce the comparator offset efficiently. Itsaves57%energy in average as compared with the conventional structure.The prototype is an8-bit50MS/s SAR ADC in SMIC65nm CMOS process.The simulation results indicate that the ADC consumes192.8μW at1.0Vsupply voltage and occupies0.018mm~2.3. The improved technique sacrifices the optimization of the lower bits andapplies the separated-capacitor switching only to the higher bits so that thecapacitance in the helper array is decreased and the overall efficiency isenhanced. It saves up to83%in power consumption with respect to theconventional technique. The prototype is an8-bit12MS/s SAR ADC in SMIC0.18μm CMOS process. The measurement results indicate that the ADCconsumes130μW at1.1V supply voltage and occupies0.1mm~2.The above simulation and testing results show obvious improvement in powerconsumption and silicon area as compared with previously published state-of-art. Theprototypes not only are fully compatible with advanced digital process and low supplyvoltage, but also prove the feasibility of the proposed technology-scaling-friendlyconcept in these two kinds of ADCs.