Research On Methodologies Of Power Analysis Attack And Cipher Chip Design For Resisting Power Analysis Attack

The cipher modules are key components of the information security system, its security level is directly related to the safety of the whole information system.21centuries ago, most of the time, the attack on the cipher module focused on the math-ematical analysis. Linear attack and differential attack were representative of the traditional cryptanalysis method. By utilizing the statistical properties of the cipher algorithm, by analyzing the selected plaintext or ciphertext to obtain the key. Such attacks generally need to acquire and process a huge amount of data, the practice is not always feasible. Thus someone started to analyze other ideas. Taking into account the actual fact that cipher chips always release some of the physical information when in working state, such as current, voltage, electromagnetic, as well as the time related information.By analyzing the physical information leakage to attack the chip, this is called side-channel attackFrom the beginning of the21st century, power analysis attack became main side-channel attack which is usually divided into three kinds:simple power analysis attack, differential power analysis attack, correlation power analysis attack. Simple power at-tack (SPA) using the relationship between the key bits in the encryption process and the actual power consumption of the chip to acquire the key information directly from the power consumption curve of the actual measurement. Differential power analysis attack (DPA) is a method by statistically analyzing large number of plaintext or cipher-text and power curves to obtain key. Correlation power analysis attack (CPA) firstly utilizes a forecast model used for cryptographic operations to draw predicted power consumption information, by correlatively comparing actual chip power consumption with predicted power consumption to infer actual key.The emergence of Power analysis theory against cipher chip has brought a lot of security issues, many literature showed examples of the successful power attacks. In this paper, we focused on several cipher algorithms to carry on power analysis research. The purpose of the study, is to find out the vulnerability of cipher algorithms,and then add countermeasures to resist the threat. Main contributions of the thesis are as follows::Power analysis platform construction:To resist the threat of power attack, countermeasures must be taken into account when realizing the cipher algorithms.In this paper, by combinating PC applications with FPGA hardware,we designed a power analysis evaluation platform. Implementation of power analysis platform based on high-performance FPGA design, not only can carry out power analysis experiments for separate cipher modules, but also has the capability to assess anti-power analysis capabilities for the design of cipher chip.RSA algorithm power analysis research and USB KEY chip design:Public key algorithm RSA is vulnerable to power analysis attacks. Firstly.by analyzing the RSA algorithm we know that the the RSA module vulnerable to power analysis attacks is due to the Modular exponentiation algorithm implementations. The basic approach to realize modular exponentiation is square-product algorithm which makes RSA each bit of key is closely related to power consumption. Attacker analyzed the consumption information then got the key.Therefore it is a great threat to the se-curity. To counter SPA and DPA attacks, we proposed a scheme by adopting random mixed modular exponentiation algorithm plus adding random pseudo-operands to re-alize modular exponentiation algorithm.The modified RSA module was implemented in FPGA and verified. Implemented on FPGA, USB Key power analysis test hard-ware platform was established. DPA attack to RSA which was based on the LR mode algorithm and fixed mixed modular exponentiation algorithm was carried out.Results showed they are easy to be attack. Finally, our proposed scheme was also tested, results showed our scheme is strong enough to sustain MESD attack.AES algorithm power analysis and high-speed cipher coprocessor de-sign:In order to design the AES algorithm module which has the ability of anti-power analysis,firstly the basic principle of AES algorithm flow, reasons for their vulnerabil-ity to power attack, as well as the corresponding attack algorithm were studied.And then we proposed our Mask covering scheme which enhanced the ability to counter power analysis attack.We completed the design of AES cipher module.Taking into ac- count the balance between security and resource,our scheme was achieved by using several fixed masks with random Selecting to achieve the purpose of approximation of random mask.In order to speed up the the AES module running speed, four pipeline design was implemented, every three clock time encryption and decryption can be done.In the design of high-speed cryptographic coprocessor, internal operation mecha-nism was parallel scheduling mechanism, thus maximized AES cryptographic module performance.The high-speed cryptographic coprocessor power analysis results showed that design with no mask protected is difficult to prevent the DPA attack, design with mask protected can effectively prevent the DPA attack.