Research On The Key Technology For High-performance Network On Chip

With the development of semiconductor technology, more and more IP cores can be integrated into a System on Chip (SoC), with hundreds of IP cores on a single chip. Conventional bus communication mode fails to meet the requirements of complex SoC in scalability, bandwidth, power, delay and reliability. Borrowing ideas from the distributed computing network communication mode, Network on Chip (NoC) technology employs routing and packet-switching to realize data communication between modules on the chip, thus effectively facilitating complex SoC communication.This dissertation analyses in detail the key technologies of NoC design and summarizes a system level NoC design approach. An in-depth study is made of NoC topology, mapping algorithm and power management on system level in an attempt to improve the performance of NoC system in power consumption, network throughput and average network delay. The major researches and the findings are:(1) A novel Pentacle NoC topology is proposed, which employs Johnson code to realize NoC node coding. Global synchronization local asynchronization strategy is used to design circular FIFO based on Johnson code. The one-hot coding of address lowers the probability of occurrence of the signal metastable state and improves the memory read/write speed. Based on the features of Pentacle topology, the shortest path routing algorithm consisting of interval routing and in-group routing is designed. Both theoretical analysis and simulation prove that the Pentacle topology is superior to2D Mesh and Octagon topology in network performance.(2) The NoC system based on Pentacle topology is verified on Xilinx FPGA to evaluate its FPGA resource occupancy. With the increase in system scale, a dramatic improvement in NoC performance can be achieved by sacrificing part of the area of Pentacle structure. Various methods for lowering the resource occupancy of the routing algorithm are discussed, and the algorithm based on Johnson code is proposed for Pentacle topology. Simulation verifies that the proposed method occupies less FPGA resources than binary-coded routing algorithm.(3) Two mapping optimization algorithms based on genetic algorithm, namely the catastrophic genetic annealing and adaptive chaos genetic annealing, are proposed for the low energy consumption mapping of NoC with bandwidth and delay constraints. A thorough study is made of the genetic coding, Boltzmann updating mechanism, cross and mutation operation, catastrophic genetics, multi-neighborhood simulated annealing and the adaptive chaos optimization strategy used in the optimization algorithm, and proper algorithm parameters are obtained through extensive experiments. In actual algorithm optimization, Boltzmann updating mechanism is introduced to select genetic individuals. The probability of an individual being selected is dynamically adjusted according to current population fitness for the algorithm search to get close to the optimal fitness thus increasing the probability of better individuals being selected; better individuals in genetic operations are optimized by multi-neighborhood simulated annealing to improve algorithm accuracy. For the population in stagnation, the catastrophic genetic annealing algorithm uses catastrophic operation to reinitialize part of worse individuals so as to jump out of a local optimum; while the adaptive chaos genetic annealing introduces adaptive chaos technique to optimize worse fitness individuals for better population diversity. Simulation shows that both algorithms have good global searching and local optimization ability, thus effectively avoiding premature convergence and improving algorithm convergence speed; and that they have higher energy efficiency than standard genetic algorithms and chaos genetic algorithms, thus significantly lowering the energy consumption of NoC system communication.(4) For energy consumption optimization of NoC with voltage frequency islands, an optimization method is proposed based on voltage frequency island partitioning, assignment and task mapping. Voltage frequency island partitioning based on processor reliability constraint is used to reduce processor energy consumption; the voltage-frequency islands assignment strategy of near convex region selection is employed to reduce the number of complex routers between different voltage islands; and NoC mapping is optimized by Quantum-behaved Particle Swarm Optimization algorithm to lower system communication energy consumption. Simulation of random communication tasks and examples of application shows that the proposed algorithm can effectively reduce the overall energy consumption of the NoC system. The introduction of multiple voltage frequency islands on the NoC platform realizes effective NoC power management while satisfying processor reliability constraints by incorporating the three strategies of voltage frequency island partitioning, voltage assignment and mapping optimization.The topology, mapping algorithm and energy consumption optimization based on voltage frequency island proposed in this dissertation provide crucial technical foundation for and a novel approach to high performance NoC system design.