Low-cost And-power Test For Digital Circuits

It is necessary to test integrated circuits products for ensuring the high yield of new product. In recent years, with the rapid development of very large scale integrated (VLSI) technique, the transistor density exponentially increases, and IC testing has become one of the greatest challenges in semiconductor industry. As a most common design for testa-bility (DFT) methodologies, full scan-based design reduces completely test generation complexity; however, it prolongs test application time and raises test power. Excessive test power dissipation and growing test cost are major issues in the testing of VLSI cir-cuits. The test cost is closely related to the test data volume and test application time. In this thesis, we research on both low power testing and test data compression, and propose several test methods that reduce the test data volume and the test power dissipation simul-taneously. Several larger ISCAS’89and ITC’99benchmark circuits have been utilized to verify these methods. The contributions of the thesis include:This thesis presents a new scan-based built-in self-testing (BIST) scheme based on capture in turn of sub-scan chains. Traditional BIST approach has some drawbacks, such as excessive power dissipation and prohibitively long test time. In the proposed scheme, each scan chain is divided into N(N>1) sub-chains. During test, using scan chain disabling technique, all sub-chains in a scan chain are active in turn in both scan shift and capture cycles, i.e. only one sub-chain is active at a time. Thus, the switching activities in the scan cells can be limited to a low level. To detect random pattern resistant faults, an algorithm of linear feedback shift register (LFSR) reseeding, which is compatible with the proposed test scheme, is presented as well. Experimental results on ISCAS’89benchmark circuits show that, compared with the conventional BIST scheme, the proposed strategy can achieve not only about (N-1)/N reductions of average and peak power, but also significant reduction of test application time and seed storage for LFSR reseeding.This thesis presents a new deterministic BIST scheme based on scan block encoding. Researching on the distributions of0,1and X-bits in test cubes, we find that there are many long test data blocks which contain only one kind of specified bits. When applying a test cube, such data blocks can be loaded with a constant value, thus shifting-in transitions degrade. The proposed scheme can also reduce the number of specified bits that need to be generated via LFSR reseeding. Therefore, test power and test data volume are significantly reduced. To further reduce the shift in power dissipation and test data volume, the thesis introduces a novel algorithm of scan-block clustering which enhances the percentage of the data blocks with no shifting-in transitions. Experimental results using Mintest set on the larger ISCAS’89benchmarks show that the proposed method reduces the switching activity significantly by72%-94%and provides a best possible test compression of74%-94%, compared with traditional deterministic BIST scheme.Power Supply Noise has significant effect on test quality of Delay testing. In the launch-on-capture (LOC) at-speed scan testing scheme, it will be sufficient to keep the peak launch power under a safe threshold since the correct operation of circuits can be guaranteed in this situation, but the shift power should be reduced as much as possible to cut down heat accumulating on the chip. This thesis presents a modified deterministic BIST scheme based on scan block encoding in linear decompressor-based test compres-sion environment. A low capture and shift-out power X-filling method compatible with the testing scheme is also proposed for simultaneous shift and capture power reduction. Interestingly, in the comprehensive strategy, capture power reduction agrees with shift-out power reduction to a certain extent. Experimental results on the larger ISCAS’89and ITC’99benchmark circuits show that the holistic strategy can reduce test power in shift cycles and capture cycles significantly under the constraint of certain compression ratio.This thesis presents DFT scheme based on selective capture and shift during test. The faults detected by a test pattern with spare specified bits can be observed by only a small fraction of scan chains though all scan chains are potential observation points. Two subsequent test cubes with certain conflicts are usually compatible in plenty of scan chains. Utilizing this fact, the proposed scheme captures test response with part of scan chains and loads new test data only into scan chains with conflicts when a new test cube is applied, thus the number of the active scan cells at a time is saved, resulting in low test power. Meanwhile, two successive test cubes share the specified bits in some scan chains, thus the encoding efficiency is improved. Experimental results on several larger ITC99benchmark circuits show that approximately50%peak power reduction and80%average power reduction during test, as well as saving of up to20%specified bits that have to be encoded by decompressor, can be obtained.