Research On High Level Mapping Techniques Of SoC Hardware/Software Co-design

Hardware/software co-design is the basis of SoC design. With the continuousincreasing development of integrate circuit, the integration degree of SoC is improved andelectric system level design (ESL) has been a hot issue in the SoC hardware/softwareco-design research. The SoC high level design is the key for ESL, including systemmodeling, hardware/software partitioning, design mapping and refining, and so on. Thisdissertation focuses on making a deep research on the high level design technologies ofESL. By introducing the technologies of application-driven design, system structuretemplate, intelligent algorithm, as well as the theory of computer support cooperative work(CSCW), we improve the existing approach of application modeling, architecture modeling,mappling algorithm and expert decision. In practice, we build a SoC transaction levelhardware/software co-design platform (TL-Platform), and finally we verify our approacheswith the real-world widely used applications. This dissertation makes four contributions asfollows:Firstly, to address the issue of application modeling, we proposed an applicationdriven SoC system level design (AD-SLD) approach. AD-SLD uses application profilingto guide SoC haredware/software co-design, which can improve the design efficiency andquality of SoC platform and chip architecture greatly. The feather of application isrecognizing for automatic system level model generation, which can ensure the consistencyand complete of system model with field specific applications. Besides, applicationanalysis ariented to SoC task partition can recongnize the information of control/data flow,computation/storage, and critical blocks in application programs. The feather requirementmodels for task partition from application profiling are used for the heuristic informationand accordance. The critical characteristic informations of PIA-CDTG are used, such aspercentage of execution time, storage requirement of max active variable, storagereqirement of object codes, data communication among nodes, paralle abibity of nodes andthe predence of nodes. An evolutationry ant colony optimization algorithm is used to the"analysis-partition"iterator optimizing for highly efficient and accirate task partition.Secondly, considering the modeling of SoC architecture, we come up with an systemstructure template based SoC transaction leve modeling and simulation (SST-TLM)approach. SST-TLM builds some application specific system structure templates intransaction level, which consist of computation IP cores, communication modules andscheduling modules. The designer use template interface to configure SoC architecture,include configure of IP core parameters, customization of communication topology andprotocol, selection of scheduling algorithm, and so on. The transaction templates supportco-simulation and performance anlaysis of computation, comuunication and scheduling,which can solve the problems of use transaction model for exploration of SoC system. The templates also support hardware/software partition, platform design space exploration, andsystem bottleneck&performance analysis. Besides the SoC communication systemstructure templates and OCP communication templates are built for communication-centricSoC applications, which support communication simulation and performance analysis.Thirdly, to process the field specific mapping issue, we put forward loop kernelpipelining mapping onto coarse-grained reconfigurable architecture (CGRA) for dataintensive applications. The CGRA supports loop self-pipelining and use the executionmode of fixed instruction multiple data for higher throughput. The higher expressionsentence of applications can be mapped onto process elements (PEs) directly bytransferring control flow dependency graph to data dependency graph. We define loopself-pipeling CGRA architecture template and show the resource sharing and pipeling ofCGRA, together with loop kernel pipeling mapping (LKPM). The experimental results frmtypical application algorithms show that the performance of our approach is close to that ofmanual mapping and optimizing. Besides, LKPM shows less resource occupation by16.3% and higher throughput by 169.1% than advanced SPKM.Finally, in the field of expert decision, we present a distributed cooperativehardware/software partition approach for multi-expert decision. We create a distributedcollaborative design environment for system decision engineers, software designers,hardware designers and application algorithm developers. The method not only utilizes theadvantages of ant colony optimization for searching global optimal solutions, but alsoprovides a framework for multi-field experts to work collaboratively. Experimental resultsshow that the method improves the quality and speed of hardware/software partition forcoarse-grained reconfigurable system design.Based on the above-mentioned studies, we build the platform hardware/softwareco-design prototype framework for SoC high level mapping (TL-Platform), which implantthe tools of application profiling, transaction level modeling and simulation,hardware/software partition. The TL-Platform system has been successfully deployed inthe projects of armed forces and embedded media SoC design.