| The extensive and deep researches of large scale integrated circuits and Micro-Electro-Mechanical (MEMS) technology promote the development of the monolithic integrated sensors. The monolithic integrated sensors are characterized by small size, light weight, low power dissipation and simple peripheral circuit and have presently become the main developing tendency of sensors. The analog to digital converter (ADC) is one of the core modules in the integrated sensor. How to optimize the system architecture and circuits to meet the requirements of high resolution, high speed and low power dissipation is the research focus, which is also a hot and difficult spot in the design of mixed-signal integrated circuits.Among all the types of ADCs, the SAR ADC andΣΔADC (theΣΔmodulator is the key component of theΣΔADC, which determines the precision of the whole ADC) are usually used in the integrated sensors. Combining the development requirements of an integrated MEMS thermal vacuum sensor, this paper deeply researches the architectures and design methods of the SAR ADC andΣΔmodulator. The low-power high-performance SAR ADC andΣΔmodulator have been designed. With consideration of the performance of the whole sensor system and the matureness and stability of the current domestic integrated circuit process, the chip is fabricated in a 0.5μm 2P3M standard CMOS process. The main works and contributions are concluded as following:(1) A 2.5 MSPS SAR ADC is designed and realized. In order to improve the sampling rate, the DAC and comparator are optimized. The circuit nonidealities are analyzed in detail, and the corresponding design techniques are researched to overcome these effects. The expression of the power dissipation is deduced to guide the low-power circuit design. The test results show that a SFDR of 68 dB and a SNR of 56.6 dB are achieved with the sinusoidal input signal of 512 kHz. The chip reaches an ENOB of 9.1. The DNL and INL are respectively 0.84 LSB and 0.86 LSB. The chip occupies an area of 1.7 mm2. The power consumption is 2.7 mW at a 3 V supply voltage. Compared with some recent SAR ADCs reported by mainland research organizations, the design in this paper has competitive sampling rate, lower power consumption, better FOM and reaches an advanced domestic level. (2) A novel second-order modulator topology is proposed. The feed-forward path is adopted to suppress the harmonic distortion and increase the dynamic range (DR). In contrast with the feed-forward modulator structures presented before, the adder is excluded from the proposed modulator. The circuit complexity and chip area are decreased. In order to meet the sensor application, the 1/f noise of the operational amplifier has to be effectively restrained. Therefore, the correlated double sampling circuit is introduced in the integrator. The effects of circuit non-idealities on the modulator performance are deeply analyzed. The mathematical model of the modulator is established to obtain the key indexes of the sub-modules by Matlab/Simulink behavioral level simulation.(3) Based on the research and comparison of the various circuit structures, the correlated double sampling circuit, operational amplifiers, comparator, capacitors, switches and the two-phase non-overlapping clock generator are designed and optimized under the consideration of resolution, speed and power dissipation. The test results indicate that the modulator achieves a peak SNR of 79.7 dB and a DR of 81 dB. The ENOB is 13 bit. The circuit dissipates 9 mW from a single 3 V power supply.In comparison with the recently reported modulators designed for the sensor systems, the proposed modulator in the paper has lower power consumption, higher FOM and better comprehensive performance.
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