For Short-range Devices With On-chip Self-calibration Receiver Realization

Short range wireless communication technique has been widely used because of having an inherent advantage in low power for its short range over other wireless communication techniques and occupying the unlicensed Industry Science Medical (ISM) frequency bands. Short range devices (SRD) have become an outstanding technique in all sorts of short range wireless communication techniques for its low power and convenience of design.This work focuses on the design of low-cost wireless receiver for SRD soperationg in the UHF band with very low power consumption. Many applications would benefit from the availability of this kind of devices, from security to remote controllers or remote medical care and health monitoring systems. All these applications are characterized by similar requirements. Firstly, their volum, including antenna and the battery, are small. Secondly, the data rate is low, at most a few tens of kilobauds over short periods of time. Thirdly, their operating distance are ranging from 1 m to 100m, which depends on the actual application.In the design process of receiver, it is focuses on the optimization of power and cost, from the selection of process, receiver structure, circuit topology to modulation scheme. Moreover, on-chip automatic calibration techniques are proposed to improve the receiver performance and ensure the bit error rate (BER).Firstly, after analysis and comparision have been done among the common receiver architectures, a low-power, low-IF and narrow band wireless receiver architecture which is suitable for SRD application is proposed in this work. Then, based on the SRD standards, the receiver design parameters are defined from the signal at the antenna and the receiver output BER, whihch are then distributed to each block design requirements.Secondly, the circuits in the receiver path are described, including low noise amplifier (LNA), down-conversion mixer, complex filter and variable gain amplifier (VGA). The LNA is designed to work at 315MHz and 433MHz. Differentaial capacitive couple common-gate structure is introduced as a noise and power optimization of the traditional common-gate amplifier. Quadraute mixer with high linearity performance is proposed. As for the image signal problem inherent in the Low-IF receiver, a 4th Butterworth Gm-C polyphase filter is used to reject the image signal. Except for the basic blocks in the receiver, this work also offers on-chip automatic calibration techniques to ensure achievable Signal-to-Noise Ratio (SNR) thus the BER, which consists of a digitally controlled, high resolution dB-linear automatic gain control (AGC), inphase (I) and quadrature (Q) gain and phase mismatch calibration, and an auto frequency calibration (AFC) of voltage-controlled oscillator (VCO). The calibration systems have a low design complexity with little power and small die area.Finally, the thesis implements a receiver for SRD applications. It has been fabricated in typical 0.25-μm CMOS process and the mainly parameters, including gain, noise figure and linearity have been tested. By comparing to the simulation results, the results have been analyzed.