Study On Optimization Design And Testing Technology Of Embedded SRAM

Embedded memories constitute a significant portion of silicon area in integrated circuit (IC). Both the number of embedded memories and their average size are increasing steadily in system on chip (SOC). Embedded random access memory (RAM), which is generally one of the densest modules in SOC, easily becomes defective in manufacturing process and therefore degrades the yield of SOC. If the power consumption of embedded RAMs reduces, the power dissipation of the whole SOC will decrease. In this thesis, a deep study of optimization of embedded static RAMs (SRAMs) for high yield and low power consumption is presented. Further, the testing technology of embedded SRAMs is also discussed. The main research results are as follows:i. Flaw types in chip manufacturing process are analyzed. From these flaw types, the changes in electricity are given and the fault models of chip are extracted. The classes of chip testing and computation of test cost have been studied. The methods of design for test (DFT) commonly used as well as the challenges of SOC testing to test engineers and design engineers are discussed.ii. In order to improve the yield of SOC, redundancy logic is added to replace faulty units in SRAM and electric-fuse box (E-fuse box) is used to store the addresses of the faulty units. The implementation of memory built-in self test (MBIST) is necessary for only once and the addresses of the faulty units are stored in E-fuse box permanently. MBIST to detect the addresses of faulty units is avoided at each power on state, thus saving testing time. K_m, the number of faulty words with max probability, is counted by means of binomial distribution and assumed to be the number of the faulty words in memory. So the optimum redundancy logic and the number of fuses have been calculated. The hardware of MUX for selection has been removed during writing SRAM, data are written into both the faulty units of SRAM and redundancy logic at the same time. When the address from outside matches one of the addresses in E-fuse box, only the data in redundancy logic are read out. As a result, a lot of hardware resources are saved.iii. Optimization technologies of common dynamic power and static power are discussed. The estimation methods of static and dynamic power consumption are also analyzed. Power consumption under only normal function mode is considered in the past, contribution of power consumption under test mode is growing to the total power consumption with the increasingly complex SOC. How to effectively reduce the power dissipation in test mode already becomes the important content in low power design. That isolation logic and power on/off states are added to reduce power consumption in test mode, an optimization method of embedded SRAM for low power, is proposed in this thesis. By adding isolation logic, the circuit is forced into low voltage state and only in existence of leakage current. Many test modes and the concept of sub-block are introduced into the circuit. Each sub-block is in power on/off state according to its actual requirement under every test mode and the total power consumption of SOC reduces.iv. The overall area of memory increases after adding redundancy logic, the number of SOC chip per wafer decreases, thus the yeild is affected. In order to describe the changes of the yield objectively the boundary factor of yield, B is introduced and furthermore the boundary point of worthy redundancy logic. B=1 has been determined. The basic structure of BIST (built in self test) is discussed, and the structure of P1500 test wrapper along with the test language is emphasized. The fundamental structure of MBIST and common test algorithms are discussed, March algorithm is also analyzed in detail.v . By starting from a real project, the SRAM64K×32 optimized is used in SOC. The overall framework of the SOC is designed and a more detailed discussion of verification technology is made. The method of model checking with Onespin tool is emphasized. How to reuse the limited number of pads to save resources is presented in the design of pad control logic by examples. Testbench with function of self checking is capable of avoiding tedious manual inspections and greatly improves the efficiency of verification. In this dissertion, the structure of DFT, basic timing and testbench codes of SRAM64K×32 are described. The pattern conversion flow with TOPS tool and corresponding scripts are given. The C Shell script used for pattern resimulation with ModelSim is presented. Synthesis with DC as well as the layout design with Astro is also discussed.vi. The test structure of whole SOC has been designed. Each implementation of all test modes is also discussed in detail. The SOC design has been successfully implemented in a Chartered 90nm CMOS process. The SOC chip occupies 5.6mm×5.6mm of die area and consumes 1997mW. All 2061 SOC chips in one wafer, with 300mm of diameter, have been tested. Each SOC chip contains an optimized SRAM64K×32, testing methods of which are discussed. In the end, the testing results are compared and analyzed. The results show that the optimization is correct and practicable.