Research Of Pipeline Replacement Methodology Based On Asynchronousreplacement

Requirements for high performance and low power have brought a great challenge for micro-processor design. Today, Itamium2 of Intel Inc. integrates about 220 million transistors with 11 functional units and can pre-fetch and launch 6 instructions per cycle. Work load has also changed a lot, from calculations of several decades ago to today's operations in many areas such as electronic business and embedded developments, etc. To achieve success in market, power consumption, speed and cost have become the core issues of micro-processor design.Synchronous circuit design is based on global clocks, and the characteristics of them have made it more and more difficult for them to be improved in performance and power consumption area. On the other hand, asynchronous circuit has merits such as low power dissipation and high performance, while the impact of great design difficulty and the lack of asynchronous resources have affected the improvement of asynchronous design greatly.This article uses both the synchronous and asynchronous design methodologies, and places emphasis on pipeline design. We propose an asynchronous pipeline design methodology based on asynchronous mapping. Basing on structure substitution, asynchronous control signals can replace the clocks of synchronous pipeline with asynchronous control signals, so as to build asynchronous design from its synchronous counterpart. By this way, design difficulties of asynchronous circuits are reduced and performance and power consumption are improved. Listed below are main innovations and developments proposed in this article.1. This article proposes the basic cells used for asynchronous mapping, which are named self-control cell. The pipeline models based on C-element and self-control cell are illustrated. Then a theory that asynchronous pipelines can achieve higher performance compared with their counterparts is proved, and the performance of asynchronous pipelines is analyzed simply.2. Based on asynchronous mapping, three types of pipeline, simple pipeline, complex pipeline and the pipeline controlled by clock-gating structure are proposed, and their replacement methodologies based on asynchronous mapping are presented.3. To realize asynchronous replacement, this article proposes a front-end design methodology based on asynchronous mapping. The biggest advantage of this flow is the avoidance the step of asynchronous synthesis, and the reduction of the design difficulty of designers.4. A 24-bit pipeline with simple pipeline structure, a complex pipeline based on super-scaler structure and ARM instruction set and a pipeline structure controlled by gated signals are realized with this flow and their performance are analyzed, in order to prove the validity of the design methodology. Where the goal of the simple pipeline design is to assure the functionality of the design flow, the goal of the complex pipeline design is to verify that asynchronous replacement puts little effect on pipeline performance, and the goal of gated pipeline design is to perform power evaluation.5. The physical realization of asynchronous pipeline is always difficult due to the lack of asynchronous EDA tools. This article proposes a back-end flow for asynchronous cell and circuit design based on the EDA tools currently used. On the basis of the flow, a 24-bit pipeline based on the simple pipeline structure is realized and analyzed.On the basis of above research, designers can utilize mature EDA tools and synchronous pipeline resources to develop asynchronous pipelines freely, which would be beneficial to the development of asynchronous design.