Research On Code Compression For Embedded Processors

With the ever increasing functional requirement of embedded software, onchip memory occupies more and more silicon area and code size reduction become a major concern for embedded processor designers. The solutions which address the code size problem can be categorized into three parts: compiler optimization, high-density instruction set and code compression. The research objects in this paper including two self-developed embedded processors(CK520, SPOCK), and heterogeneous dual-core SoC(GEM-SOC) which integrated both processors. The research focuses on following three aspects:1) High-density instruction setThe working mechanism and pros/cons of dual-mode ISA is discussed using Thumb/ MIPS 16 ISA as examples; the single-mode ISA is also analyzed using CK-core ISA as an example to show how to make trade-offs between code size and performance. Code size and performance comparison is presented between dual-mode and sing-mode ISA(ARM940T, CK520) using Powerstone benchmark suite. Experimental results show that comparison with 32-bit ARM ISA, CK520 saves 38% code size at the expense of 17% performance; comparison with 16-bit Thumb ISA, CK520 saves 9% code size and gains 15% performance.2) Code compression approachesResearch on field-partition based code compression approach: three compression steps is described in formal language, that is symbol generation, symbol modeling and symbol encoding. Correlation models play important role on compression ratio, a novel correlation model-type model, which captured the correlations between the symbols of different instruction type, is proposed. A type model and traditional position model combined code compression approach is also presented. Applying this approach to SPOCK and using OggVorbis as benchmark program, the best compression ratio achieved is 53.16% which is 12～14% better than traditional methods.Research on arithmetic-coding based code compression approach: this algorithm uses arithmetic coding in combination with markov model. Coding efficiency is ensured by arithmetic coding and complex markov model can be used to explore the bit-level correlation. A state-machine based binary arithmetic coding mechanism is discussed and results of compression ratio is analyzed with different encoder/model precisions and model parameters.3) Decompression methodsBased on field-partition approach, a low overhead hardware decompression architecture is proposed to support type, position and hybrid models. Low overhead is achieve by two-stage encoding technique: multiple distinct sets of symbols are mapped onto a single predefined set of Huffman codewords according to its frequency.A software-managed code decompression mechanism is proposed for heterogeneous dual-core SoC-GEM-SOC. The program of SPOCK processor is decompressed by high-density CK520 processor when it's loaded into on-chip program memory. The software decompressor of two code compression approach mentioned above are implemented. Experiment results on Mediabech benchmark suit show: 1. software-managed mechanism can easily achieve the best compression ratio by adjust the parameter of markov model according to different applications. 2. Field-partition based approach outperform arithmetic coding based approach both in compression ratio and software decompressor performance.