Study On Current Based Testing Technology For Digital Integrated Circuits

Integrated circuits (IC) have to be tested after being manufactured from factories. IC testing has to be done during the whole period of IC design, fabrication, encapsulation, and application. It is considered to be a very important part in 4 fields (design, fabrication, encapsulation, and testing) of IC industry, and becomes a bottleneck in the development of ICs. As estimated, up to 2012, more than 48% of good ICs will fail tests. The cost of test will be from 80% to 90% among the total cost of IC design, fabrication, encapsulation, and test.Voltage based testing and Iddq testing are typical test methods for testing digital CMOS ICs. Voltage based testing involves logic test and delay test. Logic test checks for the function of ICs while delay test checks for the timing performance of ICs. Voltage based testing can detect many defects in a simple and fast way. But, because of the weakness of the fault model used and being not able to run at-speed, voltage based testing, generally speaking, is only good at verifying IC's functions. Iddq testing has more advantage of detecting some "small" defects caused by variations in production process. Reducing testing cost effectively and guaranteeing IC's reliability is the most important merit of Iddq testing. However, Iddq testing cannot detect some defects (cross-talk fault, for example) that do not elevate Iddq as well as meets challenges from deep submicron designs.Iddt testing is another test approach that exposes faults by disposing the transient current flowing through the circuit under test. It can explore some faults that cannot be detected by voltage based testing and Iddq testing. Being a complimentary test method to the conventional voltage based testing and Iddq testing, it attracts more and more attentions from academia and industry.Even though it has been investigated for 10 years, Iddt testing is still primary and cannot be used in production. Many problems are waiting for being solved. This paper investigates Iddt testing based on average current analysis technique and gets some results. It precisely defines the concept of one cycle average transient current of CMOS digital ICs, and analyzes the relationship between average transient currents and slope of input signals, workloads, and hazards by means of SPICE simulation. The simulation results verify the idea that the average transient currents can be estimated by counting only the logical up-transitions. A new formula is then...