Energy Efficient SOC Design Techniques At Behavioral And Logical Level

SOC will be a dominant income source of semiconductor industry. As integration density increased dramatically, energy consumption has become the critical concern of SOC design. The energy consumption has a direct impact on reliability, packaging costs, cooling costs, and battery life.The thesis researches on the methodology for energy efficient SOC design. SOC has several design levels according to the design flow. The thesis covers on the higher levels including system level, software level, and synthesizable logic level. We investigate the techniques to reduce circuit switch activity, parameter design, dynamic voltage scaling and the simulation environment for verification of the above techniques.Embedded processor is the bridge between hardware and software. It is the center of SOC. Several methods to reduce the circuit switch activity are developed. Pre-visiting tag technique is used to reduce the instruction cache activity. Base address locality technique is used to reduce the data cache activity. The gated clock technique is discussed and used to instruct the microarchitecture partition.SOC design is the procedure of IP integration. Not only IP design itself should be designed carefully with low energy comsumption, but the bus architecture connecting IPs is important too. CMOS power management IP can save energy for system by supporting several power modes when integrated into SOC. Dynamic voltage scaling(DVS) design reduces more energy consumption by scaling both supply voltage and clock frequency simultaneously. Several key notes in implementing DVS architecture are studied. Parameter design methodology is adopted for specific application. An automatic parameter configuration infrastructure is proposed and local search algorithm is exploited to optimize the system in reduced iterations.Software has more responsibility to reduce energy in SOC designs than laptop applications. There are many techniques for different software levels. A novel software power management framework for dynamic voltage scaling is presented. A detail investigation shows that process state can be used as a clue to separate the process into several task units and sleep events can identify these task units to predicate the workload of future tasks. A three level alarm voltage schedule algorithm is used to reduce the deadline violation and performance jitter based on the workload prediction. After analyzing the best supply voltage quantitatively, a criterion to grade the algorithm is proposed.Simulation and verification are very important stages in SOC design. A reusable SOC verification environment for HW/SW co-simulation is built. After summarizing the power modeling method, energy monitor is proposed to record power consumption.