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Research On Key Issues And Applications Of Multi-FPGA Systems

Posted on:2012-10-11Degree:DoctorType:Dissertation
Country:ChinaCandidate:C C ZhangFull Text:PDF
GTID:1118330362954309Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Multi-FPGA systems are the systems that have multiple FPGA chips, and its connection between chips comply with definite topology structure. There are many reasons for digital systems to adopt multiple FPGAs. Firstly, the system is too large to realize with only one FPGA. Secondly, electronic application continue to extend in such as 3G LTE, super computer constructed with FPGA(such as the super computer named Maxwell in University of Edinburgh), and etc. Thirdly, The Multi-FPGA systems are often made as prototyping for ASIC(Application Specific Integrated Circuit). And the end, it can be used in some special application, such as the receiver of digital array radar, and etc.It is important to research the key technology for Multi-FPGA systems, construction of Multi-FPGA systems, and discuss its specific application. The research efforts for this paper is as follows.At first, throug comprehensive study and summary for the literatures, the paper explains the concept of Multi-FPGA systems, surveys the applications of Multi-FPGA systems, Multi-FPGA systems developing and current research situation, and discusses the need for research and development.Secondly, the paper investigates the Multi-FPGA systems structure, including interconnect and configuration structure of the systems. After analysising several common multi-FPGA systems interconnection structure, we present its features. There are two basic types of configuration structures, which are scattered distribution structure and concentration one. At present, the large capacity FPGA mainly adopts high density packaging technology, such as BGA (Ball Grid Array), which can effectively reduce the package size, improve reliability and reduce costs of the chip. Such construction provides users more I/O pins, which can effectively alleviate the inadequate problem of FPGA pins. Through the extensive use of multi-layer technology, the interconnection between nonadjacent FPGAs can be easily implemented by board wiring in different layer, the design of the systems interconnection structure should be based on these characteristics. When concerning to the configuration structure, the concentration configuration structure using single configuration chip has more advantages in hardware cost, PCB implementation, configuration management, test and commissioning multiple configurations than the scattered distribution one, so concentration configuration structure should be selected in first.Thirdly, this paper gives detailed analysis for logical partition algorithm of Multi-FPGA systems. It focus on the most typical algorithms, such as KL algorithm, FM algorithm, neural network algorithm, genetic algorithm, set covering algorithm and time division multiplexing algorithm based on virtual wires. If there exists feedback in circuit and the total delay is greater than tolerance value, there will be a logic error. In order to solve this problem, the paper proposed a modified method by improving the fitness function of traditional genetic algorithm.Fourthly, Multi-FPGA system configuration scheme and clock synchronization method will be discussed in the fourth chapter. The experimental system has been developed, in which a clock synchronization method based on DLL and a small-scale parallel configuration scheme have been studied and implemented.Fifthly, this paper investigates the pricinple of pulse radar detection and realizes a FPGA-based digital algorithm program, which can improve the performance of pulse radar detection.In the end, the paper analyses the feasibility and technical advantages for Multi-FPGA systems to use in digital array radar receiver design, and discusses their specific implementation, and designs a set of IF receiver with twenty reception elements.
Keywords/Search Tags:Multi-FPGA systems, system architecture, logic partition algorithm, configuration, pulse accumulation, digital array radar receiver
PDF Full Text Request
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