Design And Study Of Integrated Circuits For Wlan Rf Receiver

WLAN(Wireless Local Area Networks) is a combinative product of computer networking and wireless communication technology. This new type network can not only realize all the functions which conditional wired networks can provide, but also access networks by wireless information channels. WLAN is a convenient and high speed network employed in mobility, individual communications and multimedia applications, and is an effective means of accessing broadband. Problems met in wired network can be easily solved in WLAN which transmits data, sounds and videos in air. Nowadays, WLAN can transmit data in the range of decade meters to several hundred meters indoor and several decade miles outdoor. In the respect of application and prospect of WLAN, the integrated radio frequency(RF) receiver used for WLAN physical levels has a great valuable prospect. How to realize a low cost but high performance RF receiver is a challenge. The system of RF receiver requires high linearity as far as possible while high sensitivity performance has been already achieved. Therefore, the harmonic distortion can be suppressed and low BER can be met. In addition, RF receiver requires large dynamic range of radio frequency input and output, which results in good adaptability and ability of anti-interference. In early times, the integrated RF receiver circuits were fabricated in GaAs technology which can work at a high frequency and has low noise. As the developing of CMOS technology, the frequency and noise characteristics of CMOS have been improved greatly nowadays and, therefore, fabricating the RF receiver circuits in CMOS technology can be realized very well. The CMOS technology has the advantages of low cost, small area and high performance, and can be easily integrated with digital baseband circuits according with the development of SOC(System on Chip).This dissertation has deigned the integrated circuits of RF receiver for IEEE 802.11a standard and the layout based on TSMC 0.18um CMOS technology. Firstly, systematic design is introduced and mechanisms of homodyne receiver, heterodyne receiver and two-step do wn-convertor structure are analysed, then, requirements of each sub-modules are defined. There are many non-idealities in the structures mentioned above, such as noise, image frequency, nonlinearities, impedance mis-matchingwhich have been analysed in this paper. The important parameters such as noise figure(NF), image rejection ration(IRR), gain, 1dB compression(P1dB), input third-order intercept point(IIP3) are spread out. Then the architecture used for IEEE802.11a standard is decided after carefully analyzing the required characteristics. Sub-blocks including LNA, Mixer, AGC, Gm-C filter, AGC and sigma-delta ADC are therefore designed. As the first stage, passive CMOS LNA plays an important role that its noise performance, gain and linearity have a great influence to the whole chain. The second stage is mixer and its linearity, gain and noise are also key points of this paper. Gilbert unit is used as the core circuit of mixer and output signal of the locate oscillator is amplified by adding an input buffer, which makes the MOSFET work on a better switching state, then the linearity performance of mixer can be improved. Gm-C filter is used for the large bandwidth requirement. AGC, the so called Variable Gain Amplifier is used to change the gain of the chain by digital signal feedback from digital signal processing module. The main characteristics of AGC are dynamic range and gain step. Cascade differential amplifiers are used and the gain is decided by the feedback digital signal from digital base-band. The dynamic range and gain step are respectively 54dB and 1.7dB. The final stage is MASH21b-24b sigma-delta ADC. The WLAN system requires a bandwidth of 10MHz and the traditional ADC, such as pipelined ADC has a greater dissipation and occupied a larger area than sigma-delta ADC which can relax the requirements of system by its mechanism. The sigma-delta ADC reduces the noise in the interested band by noise shaping and multi-bit quantization and therefore improves the SNR and the precision of ADC. DWA is used for the non-linearity induced by multi-bit DAC。The whole layout of the circuits is designed by using Cadence Virtuoso layout Edition. DRC(Design Rule Check) and LVS (Layout Versus Schematic) have been achieved by using Diva/Dracula. When the frequency of the input signal is 5.7GHz, the whole system has a NF of 9.284dB, S11-16dB, matched impedance 50Ω, gain of the whole link 45.95dB when input bits of VGA is 10011, IIP3-16.7dB, the maxim amplitude of input-30dBm. The simulation results meet the requirements of the WLAN. The whole receiver circuits (except for PLL) have a current dissipation of 38mA and the layout occupies an area of 3 mm×3mm.