Research On The Key Techniques Of Data Triggered Architecture Based Multi-core Asynchronous Mircoprocessor

With the rapid development of VLSI technology and the great increase of app-lication requirements, the multi-core architecture has been the mostly effective approach to further improve the microprocessor performance instead of high frequency. At the same time, the problems of complex clock distribution, large clock skew and high power consumption have become serious in multi-core microprocessors. Asynchronous circuit style can solve the problems, and the multi-core asynchronous architecture beco-mes a potential solution for the multi-core microprocessor design. However, lots of new problems will emerge, including design method of asynchronous circuits, architecture of asynchronous processor cores, architecture of asynchronous on-chip interconnection, and evaluation method. The study on these theories and design techniques will provide further multi-core asynchronous microprocessors with great theoretical and practical sense.This thesis introduces a multi-core asynchronous microprocessor where multiple asynchronous processor cores based on data triggered architecture (DTA) communicate with each other through a high-performance and low-power asynchronous on-chip network. During the research on the multi-core asynchronous microprocessor, some key techniques have been well studied. First, our researches focus on the design method-ology of asynchronous circuits, which is the foundation of asynchronous circuit design. Second, we investigate the asynchronous data triggered processor core and asyn-chronous on-chip network. Based on these research works, we have finally developed a multi-core asynchronous microprocessor prototype and the power consumption is also analyzed. The primary innovative works in this thesis are listed as follows.(I) We propose an automated asynchronous circuit design flow and a power-performance optimization method. In order to improve the efficiency of asynchronous circuits design, we develop an automated design flow based on macrocell. The new flow generates asynchronous circuits from register transfer level (RTL) specifications automatically, and then each stage of datapath can be synthesized with aggressive optimization restrictions. However, there often exist power and performance problems in asynchronous pipelines. In order to solve the problems, we introduce a power and performance optimization method. In this method, features of actual operations and operands are exploited to improve performance and reduce power consumption. At last, an asynchronous DLX pipeline is implemented to validate the proposed methods.(II) We propose an asynchronous data triggered architecture and design an asynchronous microprocessor. The asynchronous data triggered architecture applies asynchronous techniques to existing data triggered architecture, and it expends less power consumption. At the same time, the architecture can achieve high performance via exploiting instruction level parallelism, data level parallelism and microoperation level parallelism. However, the distribution of control introduces some serious problems, and errors may occur because of the variable latencies of operations. In order to overcome these problems, we propose a new data source selecting (DSS) scheme to guarantee instructions run correctly. In the DDS scheme, results of functional units are first buffered and then proper results are selected accordingly. At last, an asynchronous processor is implemented to show that the asynchronous DTA with DSS scheme support runs correctly and power dissipation is reduced greatly.(III) We propose a unified buffer structure (UBS) with hierarchical bit-line buffer and design a novel asynchronous on-chip router. The proposed UBS has great flexibility with low hardware overhead. The number of virtual channels in every input channel can be regulated according to the traffic characteristics of target applications. Therefore, buffer resources are utilized efficiently. In addition, the power-gated technique can also be adopted to reduce power consumption of idle buffers. A synchronous router with UBS is first implemented to validate the merits of UBS. And then, an asynchronous router with UBS is implemented. The asynchronous router achieves lower power con-sumption and lower hardware complexity compared to traditional asynchronous routers.(IV) We propose a power model for asynchronous circuits and design a prototype of the multi-core asynchronous data triggered microprocessor. In the asynchronous power model, the power of the global clock network is replaced by the power of local handshake components. By detailed analysis of the structure of asynchronous processor core and on-chip network, two different levels of power models are employed. The instruction level power mode is used for complex components, and the architecture level power model is for simple components. And then, the power models are integrated into a simulator to investigate the power behavior of multi-core asynchronous micro-processors. The simulation shows that the power of the whole microprocessor is greatly reduced, and the method is suitable for the early stage exploration.This thesis explores the asynchronous techniques on multi-core microprocessor by investigating the asynchronous circuit design method, asynchronous processor core, asynchronous on-chip network and multi-core asynchronous prototype. The experimen-tal results demonstrate that the proposed design methods and designed asynchronous circuits are effective and can be used in the design and implementation of multi-core asynchronous microprocessors.