| Nowadays our country and the major countries in the world are in the phase of the transform from analog television to digital television. We are easy to foresee that the three dimensional television technology (3DTV) will be a new commanding point in the future development of digital television, also a hotly contested spot in industrial field. As a result of the historical reason, the development of China television industry has fallen behind the advanced countries. As the next generation digital television technology, domestic and foreign 3DTV is still in the infant stage, which is a good opportunity for synchronized development of China and overseas television industry.Based on the concept of "natural 3DTV" proposed by our research group, this paper makes research on the related key technologies. GPU acceleration and SoC implementation are proposed in the end-to-end prototype system of natural 3DTV, which owns great industrial value and strategic significance.In detail, the achievements are as follows:(1) An asymmetric edge adaptive filter (AEAF) is proposed in this paper to partially solve two puzzles in 3DTV, i.e. depth generation and hole filling. Different from other similar processing methods, one time of AEAF operation can simultaneously achieve the effect of edge correction and pre-processing of the depth maps. Thus the computing complexity can be reduced. On the one hand, based on the initial depth map obtained by simple algorithms, AEAF can achieve depth maps with comparatively accurate object edges, avoiding high computation after the introduction of depth generation method based on image and video segmentation. On the other hand, AEAF can reduce the area of holes in rendered views via asymmetric smoothing of depth maps, promising an improvement in the image quality with reduced artifacts and distortions. Experiment results in the applications of 2D-to-3D conversion and stereo matching show that a balance point is found by AEAF between the two aspects of the contradiction.(2) A novel software/hardware co-design is proposed in the video decoder, using CMD to configure instructions, realizing a software/hardware interface similar to SIMD. Compared to the traditional software/hardware interface, the proposed design can promise higher flexibility and configurable features as well as packaging sub-modules for IP design and making back-end testing and verification easy. Meanwhile, a high efficience and low cost entropy decoder is proposed. The designed mentioned above have been realized in the previous SoC design for audio and video decoder which supports multiple interfaces and standards including MPEG-1, MPEG-2, MPEG-4, H.263, H.264, RealVideo 8/9/10, AVS and JPEG. MPW has been done. The work of chip design can be the backward-compatibe component for further 3D video decoder. It supplies the feasibility for future 3DTV chip design.(3) The problem brought by DIBR technology in virtual view rendering has been partially solved. On one hand, for the high computation of DIBR, an accelerating implementation based on the parallel resources of GPU is proposed. The implementation of DIBR for rendering virtual views can meet the high-resolution real-time requirement. On the other hand, to break the high dependence of the camera parameters in DIBR, a horizontal shift algorithm based on layered disparity is proposed. This algorithm can be regarded as an approximation of DIBR in the condition of real autostereoscopic displayer under the Shift-Sensor camera model. It can be used when capturing camera parameters not included in video bitstream and be a substitution for DIBR or as a supplement.
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