Basic Research On The Fabrication Techniques Of Silicon Nanopore Arrays

As the key components of nanopore-based nucleic acid sequencing systems, solid-state nanopores have drawn more and more scientific interests all over the world. Besides acting as biosensing platforms, solid-state nanopores also display their promising applications in many other fields, such as near field optics, energy conversion and molecular separation. However, the massive production of solid-state nanopores is still challenging using existing methodologies. Firstly, the fabrication processes are inefficient and costly. Secondly, the controllability of the nanopore with respect to its shape, dimension and position, need to be further improved. In order to solve these problems, the research goal of this article was set to be massively fabricating silicon(Si) nanopore arrays using traditional microelectronic processes with low cost.For this purpose, a novel method of a combination of inductively coupled plasma(ICP) etching and wet etching method was proposed, to fabricate Si nanopore arrays. The greatest merit of this method is that the shape of the nanopore can be easily tuned by changing the length-width ratio of the wet etch window. Based on the intensive analysis of the ICP etching and the anisotropic wet etching processes, the governing equations of the nanopore dimension were established, and corresponding simulations and experiments were conducted. Using this method, square and rectangular nanopore arrays with a feature size of 38 nm were fabricated.In order to cut the fabrication cost, a controllable wet etching technique for the high-throughout fabrication of pyramidal Si nanopore arrays was put forwarded. The ICP etching process was replaced by a high-temperature wet etching, so that the cost of a 4 in. nanopore chip decreased by 80%. A special single-side-etching apparatus that enables ionic current and color feed-backs was designed and manufactured. With the help of this apparatus, the nanopore opening process became indirectly visible and controllable in real time, and the governing equations of the nanopore were significantly simplified. After intensive investigation and optimization of the wet etching processes, rectangular nanopore arrays with desired length-width ratios, as well as nanoslit arrays with feature sizes as small as 13 nm, were obtained.To further reduce the nanopore size, a simple technique for the controllable shrinkage of Si naonpore arrays using dry-oxygen oxidation, was demonstrated. The Si oxidation on the conical surfaces was carefully investigated, and a theoretical model was established based on the viscous stress. Simulations and experiments of Si nanopore shrinkage were performed, and the results were consistent with each other. Using this technique, the sizes of the pyramidal nanopores prepared with the above technique s, were further reduced to 8 nm, even closed(~0 nm).In addition, the nanopore fabrication mechanism and processes using the metal-assisted plasma etching(MaPE), were also intensively investigated. Using the optimized MaPE processes, conical Si nanopore arrays with controllable cone-angles and dimensions(~26 nm) were created. Using the Si nanopore arrays fabricated with the above methods as templates(stencils), nanostencil lithography experiments in both contact mode and non-contact mode were performed. Surface nano and micro patterns with the sizes from 82 nm to 7 μm were directly deposited on any substrates. A novel micro and nano fabrication technique was obtained.