Research And Implementation Of Highly Energy-Efficient Wireless Sensor Nodes

In recent years, with modern society’s developing and global population aging, the conventional model of health care encounters many great challenges in future. An emerging technique called Wireless Body Area Network provides the opportunity for the remote medical service between doctors and patients. This novel approach has provided a great convenience for doctors and patients. It not only improves the quality of medical services, but also lowers relatively medical expenses. In this network, the data collecting must be real-time and accurate, the monitoring is long-term and the nodes are wearable and low cost. Thus, the chip implementation of wireless sensor nodes is required to be low-cost and ulralow-power.However, the low power implementation of wireless sensor nodes faces problems and challenges as follows. Firstly, the energy efficiency is very low for processing the low-frequency signal. So how to improve energy efficiency of low frequency bio-signal processing is our first challenge. Secondly, the RF power consumption accounts for the major-power in wireless sensor nodes. How to reduce the wireless transmitted data with low cost implementation so that reduce the total power is our another challenge. Thirdly, the conventional memory can not operate at ultralow voltage. How to lower the minimum operating voltage of energy-efficient memory also is a great challenge.To solve the above problems, the thesis is devoted to the research and realization of high energy-efficient wireless sensor nodes. The main content and innovative points of this thesis are listed below.Firstly, the power optimization strategy of configurable serial and parallel computing is proposed to reduce the power consumption for low-frequency bio-signal processing. According to the low frequency characteristics, this approach adjusts the number of serial and parallel computing units for obtaining minim power cost. Test results show that the chip can reduce the energy consumption more than 90% with the proposed strategy.Secondly, an asynchronous pipeline compressive sensing encoder is implemented to realize low-cost transmitted data compression. For the first time, Quasi Delay Insensitive circuits and dual-rail asynchronous memory is used to realize hardware implementation of compressed sensing algorithm. Chip test results show that it can operate minimum voltage of 240mV and achieve 33.3% energy consumption reduction.Thirdly, a highly energy-efficient on-chip memory is implemented and considered to have higher energy efficiency. The advanced technique such as dual replica bit-line delay, read word-line sharing, fully static read circuits and non-minimum channel length in memory cell are proposed in this thesis. Test results of this work show that the minimum operation voltage is 320mV and the minimum energy consumption is 0.94pJ/cycle with 25% energy efficiency improvementLastly, the future developing trend is investigated and three research directions are proposed. The first is to establish an accurate power consumption model of wireless sensor nodes for achieving the optimization of power. The second is realizing the compressed sensing algorithm in analog way for merging the process of sampling and compressing. The third is using low-leakage devices such as MEM relay.