Keyword [nanometer] Result: 181 - 200 | Page: 10 of 10 181.  Head/disk interface tribology in the nanometer regime 182.  Analysis techniques for nanometer digital integrated circuits 183.  Robust dynamic circuits with low power and high performance for nanometer CMOS technologies 184.  Low temperature selective silicon epitaxy at the nanometer scale 185.  Design and analysis methodologies to reduce soft errors in nanometer VLSI circuits 186.  Control system design for nanometer scale positioning systems 187.  Modeling circuit delay and stability in nanometer CMOS technologies 188.  Design and integration of current-mode on-chip interconnect signaling in nanometer technologies 189.  Static power dissipation in arithmetic circuits: The nanometer domain 190.  Design studies of nanometer-gate low-noise amplifier near the limits of CMOS scaling 191.  Library-free logic synthesis of high performance IP blocks for nanometer technologies 192.  Predicting single event coupling delay in nanometer technologies 193.  myCACTI: A new cache design tool for pipelined nanometer caches 194.  Routing issues in nanometer -scale integrated circuits 195.  Design and validation of a laser-interferometry-based displacement sensor with nanometer resolution 196.  Algorithms for the scaling toward nanometer VLSI physical synthesis 197.  Timing optimization for nano-meter VLSI designs 198.  On-chip signaling techniques for nanometer VLSI designs 199.  Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs 200.  A via-configurable regular fabric for nanometer technology   <<First  <Prev  Next>  Last>>  Jump to

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